Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
This commit is contained in:
Dolu1990
parent
0cf278b04f
commit
a72c7fd0d1
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@ -2,15 +2,15 @@ package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba3.apb.{Apb3SlaveFactory, Apb3Decoder, Apb3Gpio, Apb3}
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import spinal.lib.bus.amba3.apb._
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.uart._
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import spinal.lib.io.TriStateArray
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import spinal.lib.misc.{InterruptCtrl, Timer, Prescaler}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
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import vexriscv.plugin._
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import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import scala.collection.mutable.ArrayBuffer
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@ -132,31 +132,10 @@ object MuraxConfig{
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}
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}
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case class SimpleBusCmd() extends Bundle{
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val wr = Bool
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val address = UInt(32 bits)
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val data = Bits(32 bit)
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val mask = Bits(4 bit)
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}
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case class SimpleBusRsp() extends Bundle{
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val data = Bits(32 bit)
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}
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case class SimpleBus() extends Bundle with IMasterSlave {
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val cmd = Stream(SimpleBusCmd())
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val rsp = Flow(SimpleBusRsp())
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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}
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case class Murax(config : MuraxConfig) extends Component{
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import config._
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val io = new Bundle {
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//Clocks / reset
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val asyncReset = in Bool
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@ -203,14 +182,22 @@ case class Murax(config : MuraxConfig) extends Component{
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reset = resetCtrl.systemReset,
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frequency = FixedFrequency(coreFrequency)
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)
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val debugClockDomain = ClockDomain(
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clock = io.mainClk,
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reset = resetCtrl.mainClkReset,
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frequency = FixedFrequency(coreFrequency)
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)
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val system = new ClockingArea(systemClockDomain) {
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val simpleBusConfig = SimpleBusConfig(
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addressWidth = 32,
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dataWidth = 32
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)
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//Arbiter of the cpu dBus/iBus to drive the mainBus
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//Priority to dBus, !! cmd transactions can change on the fly !!
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val mainBusArbiter = new MuraxMasterArbiter(simpleBusConfig)
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//Instanciate the CPU
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val cpu = new VexRiscv(
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@ -222,18 +209,14 @@ case class Murax(config : MuraxConfig) extends Component{
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//Checkout plugins used to instanciate the CPU to connect them to the SoC
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val timerInterrupt = False
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val externalInterrupt = False
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var iBus : IBusSimpleBus = null
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var dBus : DBusSimpleBus = null
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var debugBus : DebugExtensionBus = null
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for(plugin <- cpu.plugins) plugin match{
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case plugin : IBusSimplePlugin => iBus = plugin.iBus
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case plugin : IBusSimplePlugin => mainBusArbiter.io.iBus <> plugin.iBus
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case plugin : DBusSimplePlugin => {
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if(!pipelineDBus)
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dBus = plugin.dBus
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mainBusArbiter.io.dBus <> plugin.dBus
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else {
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dBus = cloneOf(plugin.dBus)
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dBus.cmd << plugin.dBus.cmd.halfPipe()
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dBus.rsp <> plugin.dBus.rsp
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mainBusArbiter.io.dBus.cmd << plugin.dBus.cmd.halfPipe()
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mainBusArbiter.io.dBus.rsp <> plugin.dBus.rsp
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}
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}
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case plugin : CsrPlugin => {
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@ -248,218 +231,58 @@ case class Murax(config : MuraxConfig) extends Component{
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}
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val mainBus = SimpleBus()
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//Arbiter of the cpu dBus/iBus to drive the mainBus
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//Priority to dBus, !! cmd transactions can change on the fly !!
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val mainBusArbiter = new Area{
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mainBus.cmd.valid := iBus.cmd.valid || dBus.cmd.valid
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mainBus.cmd.wr := dBus.cmd.valid && dBus.cmd.wr
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mainBus.cmd.address := dBus.cmd.valid ? dBus.cmd.address | iBus.cmd.pc
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mainBus.cmd.data := dBus.cmd.data
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mainBus.cmd.mask := dBus.cmd.size.mux(
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0 -> B"0001",
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1 -> B"0011",
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default -> B"1111"
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) |<< dBus.cmd.address(1 downto 0)
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iBus.cmd.ready := mainBus.cmd.ready && !dBus.cmd.valid
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dBus.cmd.ready := mainBus.cmd.ready
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val rspPending = RegInit(False) clearWhen(mainBus.rsp.valid)
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val rspTarget = RegInit(False)
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when(mainBus.cmd.fire && !mainBus.cmd.wr){
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rspTarget := dBus.cmd.valid
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rspPending := True
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}
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when(rspPending && !mainBus.rsp.valid){
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iBus.cmd.ready := False
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dBus.cmd.ready := False
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mainBus.cmd.valid := False
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}
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iBus.rsp.ready := mainBus.rsp.valid && !rspTarget
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iBus.rsp.inst := mainBus.rsp.data
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iBus.rsp.error := False
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dBus.rsp.ready := mainBus.rsp.valid && rspTarget
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dBus.rsp.data := mainBus.rsp.data
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dBus.rsp.error := False
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}
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//Create an SimpleBus mapped RAM
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val ram = new Area{
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val bus = SimpleBus()
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val ram = Mem(Bits(32 bits), onChipRamSize / 4)
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bus.rsp.valid := RegNext(bus.cmd.fire && !bus.cmd.wr) init(False)
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bus.rsp.data := ram.readWriteSync(
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address = (bus.cmd.address >> 2).resized,
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data = bus.cmd.data,
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enable = bus.cmd.valid,
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write = bus.cmd.wr,
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mask = bus.cmd.mask
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)
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bus.cmd.ready := True
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if(onChipRamHexFile != null){
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def readHexFile(path : String, callback : (Int, Int) => Unit): Unit ={
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import scala.io.Source
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def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
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var offset = 0
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for (line <- Source.fromFile(path).getLines) {
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if (line.charAt(0) == ':'){
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val byteCount = hToI(line, 1, 2)
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val nextAddr = hToI(line, 3, 4) + offset
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val key = hToI(line, 7, 2)
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key match {
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case 0 =>
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for(i <- 0 until byteCount){
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callback(nextAddr + i, hToI(line, 9 + i * 2, 2))
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}
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case 2 =>
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offset = hToI(line, 9, 4) << 4
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case 4 =>
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offset = hToI(line, 9, 4) << 16
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case 3 =>
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case 1 =>
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}
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}
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}
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}
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val initContent = Array.fill[BigInt](ram.wordCount)(0)
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readHexFile(onChipRamHexFile,(address,data) => {
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initContent(address >> 2) |= BigInt(data) << ((address & 3)*8)
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})
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ram.initBigInt(initContent)
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}
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}
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//Bridge simpleBus to apb
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val apbBridge = new Area{
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val simpleBus = SimpleBus()
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val apb = Apb3(
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addressWidth = 20,
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dataWidth = 32
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)
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val simpleBusStage = SimpleBus()
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simpleBusStage.cmd << (if(pipelineApbBridge) simpleBus.cmd.halfPipe() else simpleBus.cmd)
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simpleBusStage.rsp >-> simpleBus.rsp
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val state = RegInit(False)
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simpleBusStage.cmd.ready := False
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apb.PSEL(0) := simpleBusStage.cmd.valid
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apb.PENABLE := state
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apb.PWRITE := simpleBusStage.cmd.wr
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apb.PADDR := simpleBusStage.cmd.address.resized
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apb.PWDATA := simpleBusStage.cmd.data
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simpleBusStage.rsp.valid := False
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simpleBusStage.rsp.data := apb.PRDATA
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when(!state){
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state := simpleBusStage.cmd.valid
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} otherwise{
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when(apb.PREADY){
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state := False
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simpleBusStage.rsp.valid := !simpleBusStage.cmd.wr
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simpleBusStage.cmd.ready := True
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}
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}
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}
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//Connect the mainBus to all slaves (ram, apbBridge)
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val mainBusDecoder = new Area {
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val masterBus = SimpleBus()
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if(!pipelineMainBus) {
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masterBus.cmd << mainBus.cmd
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masterBus.rsp >> mainBus.rsp
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} else {
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masterBus.cmd <-< mainBus.cmd
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masterBus.rsp >> mainBus.rsp
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}
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val specification = List[(SimpleBus,SizeMapping)](
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ram.bus -> (0x00000000l, onChipRamSize kB),
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apbBridge.simpleBus -> (0xF0000000l, 1 MB)
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)
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val slaveBuses = specification.map(_._1)
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val memorySpaces = specification.map(_._2)
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val hits = for((slaveBus, memorySpace) <- specification) yield {
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val hit = memorySpace.hit(masterBus.cmd.address)
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slaveBus.cmd.valid := masterBus.cmd.valid && hit
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slaveBus.cmd.payload := masterBus.cmd.payload
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hit
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}
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val noHit = !hits.orR
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masterBus.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR || noHit
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val rspPending = RegInit(False) clearWhen(masterBus.rsp.valid) setWhen(masterBus.cmd.fire && !masterBus.cmd.wr)
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val rspNoHit = RegNext(False) init(False) setWhen(noHit)
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val rspSourceId = RegNextWhen(OHToUInt(hits), masterBus.cmd.fire)
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masterBus.rsp.valid := slaveBuses.map(_.rsp.valid).orR || (rspPending && rspNoHit)
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masterBus.rsp.payload := slaveBuses.map(_.rsp.payload).read(rspSourceId)
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when(rspPending && !masterBus.rsp.valid) { //Only one pending read request is allowed
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masterBus.cmd.ready := False
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slaveBuses.foreach(_.cmd.valid := False)
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}
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}
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val gpioACtrl = Apb3Gpio(
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gpioWidth = gpioWidth
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//****** MainBus slaves ********
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val ram = new MuraxSimpleBusRam(
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onChipRamSize = onChipRamSize,
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onChipRamHexFile = onChipRamHexFile,
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simpleBusConfig = simpleBusConfig
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)
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val apbBridge = new MuraxSimpleBusToApbBridge(
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apb3Config = Apb3Config(
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addressWidth = 20,
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dataWidth = 32
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),
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pipelineBridge = pipelineApbBridge,
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simpleBusConfig = simpleBusConfig
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)
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//******** APB peripherals *********
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val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth)
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io.gpioA <> gpioACtrl.io.gpio
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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uartCtrl.io.uart <> io.uart
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externalInterrupt setWhen(uartCtrl.io.interrupt)
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val timer = new Area{
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val apb = Apb3(
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addressWidth = 8,
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dataWidth = 32
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)
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val prescaler = Prescaler(16)
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val timerA,timerB = Timer(16)
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val busCtrl = Apb3SlaveFactory(apb)
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val prescalerBridge = prescaler.driveFrom(busCtrl,0x00)
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val timerABridge = timerA.driveFrom(busCtrl,0x40)(
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ticks = List(True, prescaler.io.overflow),
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clears = List(timerA.io.full)
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)
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val timerBBridge = timerB.driveFrom(busCtrl,0x50)(
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ticks = List(True, prescaler.io.overflow),
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clears = List(timerB.io.full)
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)
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val interruptCtrl = InterruptCtrl(2)
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val interruptCtrlBridge = interruptCtrl.driveFrom(busCtrl,0x10)
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interruptCtrl.io.inputs(0) := timerA.io.full
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interruptCtrl.io.inputs(1) := timerB.io.full
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timerInterrupt setWhen(interruptCtrl.io.pendings.orR)
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}
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val timer = new MuraxApb3Timer()
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timerInterrupt setWhen(timer.io.interrupt)
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//******** Memory mappings *********
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val apbDecoder = Apb3Decoder(
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master = apbBridge.apb,
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master = apbBridge.io.apb,
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slaves = List(
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gpioACtrl.io.apb -> (0x00000, 4 kB),
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uartCtrl.io.apb -> (0x10000, 4 kB),
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timer.apb -> (0x20000, 4 kB)
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timer.io.apb -> (0x20000, 4 kB)
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)
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)
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val mainBusDecoder = new Area {
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val logic = new MuraxSimpleBusDecoder(
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master = mainBusArbiter.io.masterBus,
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specification = List[(SimpleBus,SizeMapping)](
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ram.io.bus -> (0x00000000l, onChipRamSize kB),
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apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
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),
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pipelineMaster = pipelineMainBus
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)
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}
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}
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}
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@ -0,0 +1,228 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory}
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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import spinal.lib._
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import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus}
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case class SimpleBusConfig(addressWidth : Int, dataWidth : Int)
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case class SimpleBusCmd(config : SimpleBusConfig) extends Bundle{
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val wr = Bool
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val address = UInt(config.addressWidth bits)
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val data = Bits(config.dataWidth bits)
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val mask = Bits(4 bit)
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}
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case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{
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val data = Bits(config.dataWidth bits)
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}
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case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave {
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val cmd = Stream(SimpleBusCmd(config))
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val rsp = Flow(SimpleBusRsp(config))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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}
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class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
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val io = new Bundle{
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val iBus = slave(IBusSimpleBus(false))
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val dBus = slave(DBusSimpleBus())
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val masterBus = master(SimpleBus(simpleBusConfig))
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}
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io.masterBus.cmd.valid := io.iBus.cmd.valid || io.dBus.cmd.valid
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io.masterBus.cmd.wr := io.dBus.cmd.valid && io.dBus.cmd.wr
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io.masterBus.cmd.address := io.dBus.cmd.valid ? io.dBus.cmd.address | io.iBus.cmd.pc
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io.masterBus.cmd.data := io.dBus.cmd.data
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io.masterBus.cmd.mask := io.dBus.cmd.size.mux(
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0 -> B"0001",
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1 -> B"0011",
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default -> B"1111"
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) |<< io.dBus.cmd.address(1 downto 0)
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io.iBus.cmd.ready := io.masterBus.cmd.ready && !io.dBus.cmd.valid
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io.dBus.cmd.ready := io.masterBus.cmd.ready
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val rspPending = RegInit(False) clearWhen(io.masterBus.rsp.valid)
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val rspTarget = RegInit(False)
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when(io.masterBus.cmd.fire && !io.masterBus.cmd.wr){
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rspTarget := io.dBus.cmd.valid
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rspPending := True
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}
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when(rspPending && !io.masterBus.rsp.valid){
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io.iBus.cmd.ready := False
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io.dBus.cmd.ready := False
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io.masterBus.cmd.valid := False
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}
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io.iBus.rsp.ready := io.masterBus.rsp.valid && !rspTarget
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io.iBus.rsp.inst := io.masterBus.rsp.data
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io.iBus.rsp.error := False
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io.dBus.rsp.ready := io.masterBus.rsp.valid && rspTarget
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io.dBus.rsp.data := io.masterBus.rsp.data
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io.dBus.rsp.error := False
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}
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class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
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val io = new Bundle{
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val bus = slave(SimpleBus(simpleBusConfig))
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}
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val ram = Mem(Bits(32 bits), onChipRamSize / 4)
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io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.wr) init(False)
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io.bus.rsp.data := ram.readWriteSync(
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address = (io.bus.cmd.address >> 2).resized,
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data = io.bus.cmd.data,
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enable = io.bus.cmd.valid,
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write = io.bus.cmd.wr,
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mask = io.bus.cmd.mask
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)
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io.bus.cmd.ready := True
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if(onChipRamHexFile != null){
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def readHexFile(path : String, callback : (Int, Int) => Unit): Unit ={
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import scala.io.Source
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def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
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var offset = 0
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||||
for (line <- Source.fromFile(path).getLines) {
|
||||
if (line.charAt(0) == ':'){
|
||||
val byteCount = hToI(line, 1, 2)
|
||||
val nextAddr = hToI(line, 3, 4) + offset
|
||||
val key = hToI(line, 7, 2)
|
||||
key match {
|
||||
case 0 =>
|
||||
for(i <- 0 until byteCount){
|
||||
callback(nextAddr + i, hToI(line, 9 + i * 2, 2))
|
||||
}
|
||||
case 2 =>
|
||||
offset = hToI(line, 9, 4) << 4
|
||||
case 4 =>
|
||||
offset = hToI(line, 9, 4) << 16
|
||||
case 3 =>
|
||||
case 1 =>
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
val initContent = Array.fill[BigInt](ram.wordCount)(0)
|
||||
readHexFile(onChipRamHexFile,(address,data) => {
|
||||
initContent(address >> 2) |= BigInt(data) << ((address & 3)*8)
|
||||
})
|
||||
ram.initBigInt(initContent)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, simpleBusConfig : SimpleBusConfig) extends Component{
|
||||
assert(apb3Config.dataWidth == simpleBusConfig.dataWidth)
|
||||
|
||||
val io = new Bundle {
|
||||
val simpleBus = slave(SimpleBus(simpleBusConfig))
|
||||
val apb = master(Apb3(apb3Config))
|
||||
}
|
||||
|
||||
val simpleBusStage = SimpleBus(simpleBusConfig)
|
||||
simpleBusStage.cmd << (if(pipelineBridge) io.simpleBus.cmd.halfPipe() else io.simpleBus.cmd)
|
||||
simpleBusStage.rsp >-> io.simpleBus.rsp
|
||||
|
||||
val state = RegInit(False)
|
||||
simpleBusStage.cmd.ready := False
|
||||
|
||||
io.apb.PSEL(0) := simpleBusStage.cmd.valid
|
||||
io.apb.PENABLE := state
|
||||
io.apb.PWRITE := simpleBusStage.cmd.wr
|
||||
io.apb.PADDR := simpleBusStage.cmd.address.resized
|
||||
io.apb.PWDATA := simpleBusStage.cmd.data
|
||||
|
||||
simpleBusStage.rsp.valid := False
|
||||
simpleBusStage.rsp.data := io.apb.PRDATA
|
||||
when(!state) {
|
||||
state := simpleBusStage.cmd.valid
|
||||
} otherwise {
|
||||
when(io.apb.PREADY){
|
||||
state := False
|
||||
simpleBusStage.rsp.valid := !simpleBusStage.cmd.wr
|
||||
simpleBusStage.cmd.ready := True
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class MuraxSimpleBusDecoder(master : SimpleBus, specification : List[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
|
||||
val masterPipelined = SimpleBus(master.config)
|
||||
if(!pipelineMaster) {
|
||||
masterPipelined.cmd << master.cmd
|
||||
masterPipelined.rsp >> master.rsp
|
||||
} else {
|
||||
masterPipelined.cmd <-< master.cmd
|
||||
masterPipelined.rsp >> master.rsp
|
||||
}
|
||||
|
||||
val slaveBuses = specification.map(_._1)
|
||||
val memorySpaces = specification.map(_._2)
|
||||
|
||||
val hits = for((slaveBus, memorySpace) <- specification) yield {
|
||||
val hit = memorySpace.hit(masterPipelined.cmd.address)
|
||||
slaveBus.cmd.valid := masterPipelined.cmd.valid && hit
|
||||
slaveBus.cmd.payload := masterPipelined.cmd.payload
|
||||
hit
|
||||
}
|
||||
val noHit = !hits.orR
|
||||
masterPipelined.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR || noHit
|
||||
|
||||
val rspPending = RegInit(False) clearWhen(masterPipelined.rsp.valid) setWhen(masterPipelined.cmd.fire && !masterPipelined.cmd.wr)
|
||||
val rspNoHit = RegNext(False) init(False) setWhen(noHit)
|
||||
val rspSourceId = RegNextWhen(OHToUInt(hits), masterPipelined.cmd.fire)
|
||||
masterPipelined.rsp.valid := slaveBuses.map(_.rsp.valid).orR || (rspPending && rspNoHit)
|
||||
masterPipelined.rsp.payload := slaveBuses.map(_.rsp.payload).read(rspSourceId)
|
||||
|
||||
when(rspPending && !masterPipelined.rsp.valid) { //Only one pending read request is allowed
|
||||
masterPipelined.cmd.ready := False
|
||||
slaveBuses.foreach(_.cmd.valid := False)
|
||||
}
|
||||
}
|
||||
|
||||
class MuraxApb3Timer extends Component{
|
||||
val io = new Bundle {
|
||||
val apb = slave(Apb3(
|
||||
addressWidth = 8,
|
||||
dataWidth = 32
|
||||
))
|
||||
val interrupt = out Bool
|
||||
}
|
||||
|
||||
val prescaler = Prescaler(16)
|
||||
val timerA,timerB = Timer(16)
|
||||
|
||||
val busCtrl = Apb3SlaveFactory(io.apb)
|
||||
val prescalerBridge = prescaler.driveFrom(busCtrl,0x00)
|
||||
|
||||
val timerABridge = timerA.driveFrom(busCtrl,0x40)(
|
||||
ticks = List(True, prescaler.io.overflow),
|
||||
clears = List(timerA.io.full)
|
||||
)
|
||||
|
||||
val timerBBridge = timerB.driveFrom(busCtrl,0x50)(
|
||||
ticks = List(True, prescaler.io.overflow),
|
||||
clears = List(timerB.io.full)
|
||||
)
|
||||
|
||||
val interruptCtrl = InterruptCtrl(2)
|
||||
val interruptCtrlBridge = interruptCtrl.driveFrom(busCtrl,0x10)
|
||||
interruptCtrl.io.inputs(0) := timerA.io.full
|
||||
interruptCtrl.io.inputs(1) := timerB.io.full
|
||||
io.interrupt := interruptCtrl.io.pendings.orR
|
||||
}
|
||||
Loading…
Reference in New Issue