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VexRiscv
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Fix FetchPlugin redo gen condition 

Fix injectorFailure reset
This commit is contained in:
Charles Papon 2020-02-18 01:00:11 +01:00
parent f63c4db469
commit a7440426fd
1 changed files with 7 additions and 5 deletions
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12
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -129,7 +129,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
val inc = RegInit(False) clearWhen(corrected || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready) val inc = RegInit(False) clearWhen(corrected || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready)
val pc = pcReg + (inc ## B"00").asUInt val pc = pcReg + (inc ## B"00").asUInt
val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits))) val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
val redo = fetchRedoGen generate Flow(UInt(32 bits)) val redo = (fetchRedoGen || prediction == DYNAMIC_TARGET) generate Flow(UInt(32 bits))
val flushed = False val flushed = False
if(compressedGen) when(inc) { if(compressedGen) when(inc) {
@ -142,7 +142,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
pc := predictionPcLoad.payload pc := predictionPcLoad.payload
} }
} }
if(fetchRedoGen) when(redo.valid){ if(redo != null) when(redo.valid){
corrected := True corrected := True
pc := redo.payload pc := redo.payload
flushed := True flushed := True
@ -216,8 +216,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
s.output << s.input.haltWhen(s.halt) s.output << s.input.haltWhen(s.halt)
} }
fetchPc.redo.valid := redoFetch if(fetchPc.redo != null) {
fetchPc.redo.payload := stages.last.input.payload fetchPc.redo.valid := redoFetch
fetchPc.redo.payload := stages.last.input.payload
}
stages.head.flush := False //getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush stages.head.flush := False //getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
for((s,sNext) <- (stages, stages.tail).zipped) { for((s,sNext) <- (stages, stages.tail).zipped) {
@ -579,7 +581,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1) val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt) val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready) val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready, init=False)
val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
when(injectorFailure || bypassFailure){ when(injectorFailure || bypassFailure){