Fix FetchPlugin redo gen condition
Fix injectorFailure reset
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f63c4db469
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@ -129,7 +129,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val inc = RegInit(False) clearWhen(corrected || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready)
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val pc = pcReg + (inc ## B"00").asUInt
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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val redo = fetchRedoGen generate Flow(UInt(32 bits))
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val redo = (fetchRedoGen || prediction == DYNAMIC_TARGET) generate Flow(UInt(32 bits))
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val flushed = False
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if(compressedGen) when(inc) {
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@ -142,7 +142,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pc := predictionPcLoad.payload
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}
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}
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if(fetchRedoGen) when(redo.valid){
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if(redo != null) when(redo.valid){
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corrected := True
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pc := redo.payload
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flushed := True
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@ -216,8 +216,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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s.output << s.input.haltWhen(s.halt)
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}
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if(fetchPc.redo != null) {
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fetchPc.redo.valid := redoFetch
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fetchPc.redo.payload := stages.last.input.payload
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}
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stages.head.flush := False //getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
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for((s,sNext) <- (stages, stages.tail).zipped) {
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@ -579,7 +581,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
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val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
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val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
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val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
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val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready, init=False)
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val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
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when(injectorFailure || bypassFailure){
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