Add haltItByOther

Axi4, remove some pipelining

src/main/scala/SpinalRiscv/Pipeline.scala

@@ -117,7 +117,7 @@ trait Pipeline {
     }
 
     for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
-      stage.arbitration.isStuckByOthers := stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltIt/* && !s.arbitration.removeIt*/).foldLeft(False)(_ || _)
+      stage.arbitration.isStuckByOthers := stage.arbitration.haltItByOther || stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltIt/* && !s.arbitration.removeIt*/).foldLeft(False)(_ || _)
       stage.arbitration.isStuck := stage.arbitration.haltIt || stage.arbitration.isStuckByOthers
       stage.arbitration.isFiring := stage.arbitration.isValid && !stage.arbitration.isStuck && !stage.arbitration.removeIt
     }

src/main/scala/SpinalRiscv/Plugin/CsrPlugin.scala

@@ -261,7 +261,7 @@ class CsrPlugin(config : MachineCsrConfig) extends Plugin[VexRiscv] with Excepti
       //Used to make the pipeline empty softly (for interrupts)
       val pipelineLiberator = new Area{
         val enable = False
-        prefetch.arbitration.haltIt setWhen(enable)
+        prefetch.arbitration.haltItByOther setWhen(enable)
         val done = ! List(fetch, decode, execute, memory).map(_.arbitration.isValid).orR
       }
 

src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala

@@ -46,7 +46,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
     slave(rsp)
   }
 
-  def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = {
+  def toAxi4Shared(stageCmd : Boolean = true): Axi4Shared = {
     val axi = Axi4Shared(DBusSimpleBus.getAxi4Config())
     val pendingWritesMax = 7
     val pendingWrites = CounterUpDown(
@@ -55,7 +55,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
       decWhen = axi.writeRsp.fire
     )
 
-    val cmdPreFork = if (stageCmd) cmd.stage.stage() else cmd
+    val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
     val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && !cmdPreFork.wr) || pendingWrites === pendingWritesMax))
     axi.sharedCmd.arbitrationFrom(cmdFork)
     axi.sharedCmd.write := cmdFork.wr
@@ -85,11 +85,11 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
 
     //TODO remove
     val axi2 = Axi4Shared(DBusSimpleBus.getAxi4Config())
-    axi.arw >/-> axi2.arw
-    axi.w >/-> axi2.w
-    axi.r <-/< axi2.r
-    axi.b <-/< axi2.b
-
+//    axi.arw >/-> axi2.arw
+//    axi.w >/-> axi2.w
+//    axi.r <-/< axi2.r
+//    axi.b <-/< axi2.b
+    axi2 << axi
     axi2
   }
 }

src/main/scala/SpinalRiscv/Plugin/DebugPlugin.scala

@@ -141,7 +141,7 @@ class DebugPlugin(debugClockDomain : ClockDomain) extends Plugin[VexRiscv] {
 
 
       when(execute.arbitration.isFiring && execute.input(IS_EBREAK)) {
-        prefetch.arbitration.haltIt := True
+        prefetch.arbitration.haltItByOther := True
         decode.arbitration.flushAll := True
         haltIt := True
         haltedByBreak := True

src/main/scala/SpinalRiscv/Plugin/IBusSimplePlugin.scala

@@ -63,8 +63,9 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
 
     //TODO remove
     val axi2 = Axi4ReadOnly(IBusSimpleBus.getAxi4Config())
-    axi.ar >/-> axi2.ar
-    axi.r <-/< axi2.r
+//    axi.ar >/-> axi2.ar
+//    axi.r <-/< axi2.r
+    axi2 << axi
     axi2
   }
 }
@@ -88,9 +89,9 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
     val pendingCmd = RegInit(False) clearWhen(iBus.rsp.ready) setWhen(iBus.cmd.fire)
 
     //Emit iBus.cmd request
-    iBus.cmd.valid := prefetch.arbitration.isFiring //prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers
+    iBus.cmd.valid := prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers && !(pendingCmd && !iBus.rsp.ready)//prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers
     iBus.cmd.pc := prefetch.output(PC)
-    prefetch.arbitration.haltIt setWhen(!iBus.cmd.ready || (pendingCmd && !iBus.rsp.ready)) //TODO rework arbitration of iBusCmdvalid and halt it
+    prefetch.arbitration.haltIt setWhen(!iBus.cmd.ready || (pendingCmd && !iBus.rsp.ready))
 
 
     //Bus rsp buffer

src/main/scala/SpinalRiscv/Stage.scala

@@ -46,6 +46,7 @@ class Stage() extends Area{
 
   val arbitration = new Area{
     val haltIt = False
+    val haltItByOther = False
     val removeIt = False
     val flushAll = False
     val isValid = RegInit(False)

src/main/scala/SpinalRiscv/TopLevel.scala

@@ -291,8 +291,8 @@ object TopLevel {
         )
       )
 
-//      val toplevel = new VexRiscv(configFull)
-      val toplevel = new VexRiscv(configLight)
+      val toplevel = new VexRiscv(configFull)
+//      val toplevel = new VexRiscv(configLight)
 //      val toplevel = new VexRiscv(configTest)
       toplevel.decode.input(toplevel.config.INSTRUCTION).addAttribute(Verilator.public)
       toplevel.decode.input(toplevel.config.PC).addAttribute(Verilator.public)

src/main/scala/SpinalRiscv/demo/Briey.scala

@@ -298,16 +298,6 @@ object Briey{
     val config = SpinalConfig().dumpWave()
     config.generateVerilog({
       val toplevel = new Briey(BrieyConfig.default)
-      /*toplevel.axi.ram.ram.initialContent = new Array[BigInt](toplevel.axi.ram.ram.wordCount)
-      toplevel.axi.ram.ram.initialContent(0) = 0x00000013
-      toplevel.axi.ram.ram.initialContent(1) = 0x10000013
-      toplevel.axi.ram.ram.initialContent(2) = 0x20000013
-      toplevel.axi.ram.ram.initialContent(3) = 0x30000013
-      toplevel.axi.ram.ram.initialContent(4) = 0x40000013
-      toplevel.axi.ram.ram.initialContent(5) = 0x50000013
-      toplevel.axi.ram.ram.initialContent(6) = 0x60000013
-      toplevel.axi.ram.ram.initialContent(7) = 0x70000013*/
-      
       toplevel
     })
   }

src/test/cpp/regression/makefile

@@ -3,7 +3,7 @@ DBUS=DBUS_SIMPLE
 TRACE?=no
 TRACE_ACCESS?=no
 TRACE_START=0
-CSR=no
+CSR=yes
 MMU=no
 DEBUG_PLUGIN=yes
 DEBUG_PLUGIN_EXTERNAL?=no