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Add tap less debug plugin bridges

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This commit is contained in:
Dolu1990 2020-04-19 17:56:26 +02:00
parent ebe070f9dd
commit ad2d2e411a
1 changed files with 29 additions and 9 deletions
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38
src/main/scala/vexriscv/plugin/DebugPlugin.scala
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@ -1,7 +1,7 @@
package vexriscv.plugin package vexriscv.plugin
import spinal.lib.com.jtag.Jtag import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
import spinal.lib.system.debugger.{JtagBridge, SystemDebugger, SystemDebuggerConfig} import spinal.lib.system.debugger.{JtagBridge, JtagBridgeNoTap, SystemDebugger, SystemDebuggerConfig, SystemDebuggerMemBus}
import vexriscv.plugin.IntAluPlugin.{ALU_CTRL, AluCtrlEnum} import vexriscv.plugin.IntAluPlugin.{ALU_CTRL, AluCtrlEnum}
import vexriscv._ import vexriscv._
import vexriscv.ip._ import vexriscv.ip._
@ -63,6 +63,18 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
bus bus
} }
def from(c : SystemDebuggerConfig) : SystemDebuggerMemBus = {
val mem = SystemDebuggerMemBus(c)
cmd.valid := mem.cmd.valid
cmd.wr := mem.cmd.wr
cmd.data := mem.cmd.data
cmd.address := mem.cmd.address.resized
mem.cmd.ready := cmd.ready
mem.rsp.valid := RegNext(cmd.fire).init(False)
mem.rsp.payload := rsp.data
mem
}
def fromJtag(): Jtag ={ def fromJtag(): Jtag ={
val jtagConfig = SystemDebuggerConfig( val jtagConfig = SystemDebuggerConfig(
memAddressWidth = 32, memAddressWidth = 32,
@ -72,16 +84,24 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
val jtagBridge = new JtagBridge(jtagConfig) val jtagBridge = new JtagBridge(jtagConfig)
val debugger = new SystemDebugger(jtagConfig) val debugger = new SystemDebugger(jtagConfig)
debugger.io.remote <> jtagBridge.io.remote debugger.io.remote <> jtagBridge.io.remote
debugger.io.mem.cmd.valid <> cmd.valid debugger.io.mem <> this.from(jtagConfig)
debugger.io.mem.cmd.ready <> cmd.ready
debugger.io.mem.cmd.wr <> cmd.wr
cmd.address := debugger.io.mem.cmd.address.resized
debugger.io.mem.cmd.data <> cmd.data
debugger.io.mem.rsp.valid <> RegNext(cmd.fire).init(False)
debugger.io.mem.rsp.payload <> rsp.data
jtagBridge.io.jtag jtagBridge.io.jtag
} }
def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={
val jtagConfig = SystemDebuggerConfig(
memAddressWidth = 32,
memDataWidth = 32,
remoteCmdWidth = 1
)
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
val debugger = new SystemDebugger(jtagConfig)
debugger.io.remote <> jtagBridge.io.remote
debugger.io.mem <> this.from(jtagConfig)
jtagBridge.io.ctrl
}
} }
case class DebugExtensionIo() extends Bundle with IMasterSlave{ case class DebugExtensionIo() extends Bundle with IMasterSlave{