Add tap less debug plugin bridges
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@ -1,7 +1,7 @@
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package vexriscv.plugin
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.system.debugger.{JtagBridge, SystemDebugger, SystemDebuggerConfig}
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import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
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import spinal.lib.system.debugger.{JtagBridge, JtagBridgeNoTap, SystemDebugger, SystemDebuggerConfig, SystemDebuggerMemBus}
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import vexriscv.plugin.IntAluPlugin.{ALU_CTRL, AluCtrlEnum}
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import vexriscv._
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import vexriscv.ip._
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@ -63,6 +63,18 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
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bus
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}
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def from(c : SystemDebuggerConfig) : SystemDebuggerMemBus = {
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val mem = SystemDebuggerMemBus(c)
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cmd.valid := mem.cmd.valid
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cmd.wr := mem.cmd.wr
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cmd.data := mem.cmd.data
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cmd.address := mem.cmd.address.resized
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mem.cmd.ready := cmd.ready
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mem.rsp.valid := RegNext(cmd.fire).init(False)
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mem.rsp.payload := rsp.data
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mem
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}
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def fromJtag(): Jtag ={
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val jtagConfig = SystemDebuggerConfig(
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memAddressWidth = 32,
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@ -72,16 +84,24 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
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val jtagBridge = new JtagBridge(jtagConfig)
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val debugger = new SystemDebugger(jtagConfig)
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debugger.io.remote <> jtagBridge.io.remote
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debugger.io.mem.cmd.valid <> cmd.valid
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debugger.io.mem.cmd.ready <> cmd.ready
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debugger.io.mem.cmd.wr <> cmd.wr
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cmd.address := debugger.io.mem.cmd.address.resized
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debugger.io.mem.cmd.data <> cmd.data
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debugger.io.mem.rsp.valid <> RegNext(cmd.fire).init(False)
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debugger.io.mem.rsp.payload <> rsp.data
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debugger.io.mem <> this.from(jtagConfig)
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jtagBridge.io.jtag
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}
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def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={
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val jtagConfig = SystemDebuggerConfig(
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memAddressWidth = 32,
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memDataWidth = 32,
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remoteCmdWidth = 1
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)
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val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
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val debugger = new SystemDebugger(jtagConfig)
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debugger.io.remote <> jtagBridge.io.remote
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debugger.io.mem <> this.from(jtagConfig)
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jtagBridge.io.ctrl
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}
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}
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case class DebugExtensionIo() extends Bundle with IMasterSlave{
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