Got the new MMU design to pass simple tests #60
This commit is contained in:
Dolu1990
parent
ea56481ead
commit
af2acbd46e
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@ -44,9 +44,16 @@ trait Pipeline {
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plugins.foreach(_.pipeline = this.asInstanceOf[T])
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plugins.foreach(_.setup(this.asInstanceOf[T]))
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plugins.foreach{ p =>
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p.parentScope = Component.current.dslBody //Put the given plugin as a child of the current component
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p.reflectNames()
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}
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//Build plugins
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plugins.foreach(_.build(this.asInstanceOf[T]))
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//Interconnect stages
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class KeyInfo{
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var insertStageId = Int.MaxValue
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@ -170,7 +170,7 @@ object LinuxGen {
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)
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)
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if(withMmu) config.plugins += new MmuPlugin(
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virtualRange = _(31 downto 28) === 0xC,
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virtualRange = a => True,
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ioRange = _(31 downto 28) === 0xF,
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allowUserIo = true
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)
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@ -109,7 +109,7 @@ object CsrPluginConfig{
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sbadaddrAccess = CsrAccess.READ_WRITE,
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scycleAccess = CsrAccess.READ_WRITE,
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sinstretAccess = CsrAccess.READ_WRITE,
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satpAccess = CsrAccess.READ_WRITE,
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satpAccess = CsrAccess.NONE, //Implemented into the MMU plugin
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medelegAccess = CsrAccess.READ_WRITE,
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midelegAccess = CsrAccess.READ_WRITE,
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pipelineCsrRead = false,
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@ -643,7 +643,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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})
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val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) < pipeline.indexOf(b.stage))
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sortedByStage.zipWithIndex.foreach(e => e._1.port.setName(e._1.stage.getName() + "_exception_agregat"))
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// sortedByStage.zipWithIndex.foreach(e => e._1.port.setName(e._1.stage.getName() + "_exception_agregat"))
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exceptionValids := exceptionValidsRegs
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for(portInfo <- sortedByStage; port = portInfo.port ; stage = portInfo.stage; stageId = indexOf(portInfo.stage)) {
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when(port.valid) {
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@ -223,7 +223,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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var redoBranch : Flow[UInt] = null
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val catchSomething = catchAccessFault || catchAddressMisaligned || memoryTranslatorPortConfig != null
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var dBusAccess : DBusAccess = null
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@dontName var dBusAccess : DBusAccess = null
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override def newDBusAccess(): DBusAccess = {
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assert(dBusAccess == null)
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dBusAccess = DBusAccess()
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@ -383,6 +383,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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if(catchSomething) memoryExceptionPort.valid := False
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if(memoryTranslatorPortConfig != null) redoBranch.valid := False
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}
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arbitration.flushAll setWhen(redoBranch.valid)
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}
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@ -607,8 +607,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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def stageXToIBusRsp[T <: Data](stage : Any, input : T): (T) ={
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iBusRsp.stages.dropWhile(_ != stage).foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready))
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iBusRsp.stages.dropWhile(_ != stage).tail.foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready))
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}
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}
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@ -305,6 +305,8 @@ class IBusSimplePlugin(resetVector : BigInt,
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redoBranch.payload := stages.last.input.payload
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}
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decode.arbitration.flushAll setWhen(redoBranch.valid)
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if(catchSomething){
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decodeExceptionPort.code.assignDontCare()
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decodeExceptionPort.badAddr := join.pc //TODO Should it be the physical address insted ?
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@ -315,7 +317,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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}
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if(memoryTranslatorPortConfig != null) {
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val privilegeService = pipeline.serviceElse(classOf[PrivilegeService], PrivilegeServiceDefault())
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when(stages.last.input.valid && (mmu.joinCtx.exception || !mmu.joinCtx.allowExecute || (!mmu.joinCtx.allowUser && privilegeService.isUser(decode)))){
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when(stages.last.input.valid && !mmu.joinCtx.refilling && (mmu.joinCtx.exception || !mmu.joinCtx.allowExecute || (!mmu.joinCtx.allowUser && privilegeService.isUser(decode)))){
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decodeExceptionPort.code := 12
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exceptionDetected := True
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}
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@ -42,7 +42,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
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allowUserIo : Boolean,
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allowMachineModeMmu : Boolean = false) extends Plugin[VexRiscv] with MemoryTranslator {
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var dBus : DBusAccess = null
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var dBusAccess : DBusAccess = null
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val portsInfo = ArrayBuffer[MmuPort]()
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override def newTranslationPort(priority : Int,args : Any): MemoryTranslatorBus = {
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@ -61,7 +61,7 @@ class MmuPlugin(virtualRange : UInt => Bool,
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decoderService.add(SFENCE_VMA, List(IS_SFENCE_VMA -> True))
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dBus = pipeline.service(classOf[DBusAccessService]).newDBusAccess()
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dBusAccess = pipeline.service(classOf[DBusAccessService]).newDBusAccess()
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}
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override def build(pipeline: VexRiscv): Unit = {
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@ -142,19 +142,19 @@ class MmuPlugin(virtualRange : UInt => Bool,
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}
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val dBusRsp = new Area{
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val pte = PTE()
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pte.assignFromBits(dBus.rsp.data)
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val exception = !pte.V || (!pte.R && pte.W) || dBus.rsp.error
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pte.assignFromBits(dBusAccess.rsp.data)
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val exception = !pte.V || (!pte.R && pte.W) || dBusAccess.rsp.error
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val leaf = pte.R || pte.X
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}
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val pteBuffer = RegNextWhen(dBusRsp.pte, dBus.rsp.valid)
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val pteBuffer = RegNextWhen(dBusRsp.pte, dBusAccess.rsp.valid)
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dBus.cmd.valid := False
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dBus.cmd.write := False
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dBus.cmd.size := 2
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dBus.cmd.address.assignDontCare()
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dBus.cmd.data.assignDontCare()
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dBus.cmd.writeMask.assignDontCare()
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dBusAccess.cmd.valid := False
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dBusAccess.cmd.write := False
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dBusAccess.cmd.size := 2
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dBusAccess.cmd.address.assignDontCare()
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dBusAccess.cmd.data.assignDontCare()
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dBusAccess.cmd.writeMask.assignDontCare()
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switch(state){
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is(State.IDLE){
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for(port <- portsInfo.sortBy(_.priority)){
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@ -168,14 +168,14 @@ class MmuPlugin(virtualRange : UInt => Bool,
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}
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}
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is(State.L1_CMD){
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dBus.cmd.valid := True
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dBus.cmd.address := satp.ppn @@ vpn1 @@ U"00"
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when(dBus.cmd.ready){
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dBusAccess.cmd.valid := True
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dBusAccess.cmd.address := satp.ppn @@ vpn1 @@ U"00"
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when(dBusAccess.cmd.ready){
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state := State.L1_RSP
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}
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}
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is(State.L1_RSP){
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when(dBus.rsp.valid){
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when(dBusAccess.rsp.valid){
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when(dBusRsp.leaf || dBusRsp.exception){
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state := State.IDLE
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} otherwise {
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@ -184,20 +184,20 @@ class MmuPlugin(virtualRange : UInt => Bool,
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}
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}
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is(State.L0_CMD){
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dBus.cmd.valid := True
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dBus.cmd.address := pteBuffer.PPN1(9 downto 0) @@ pteBuffer.PPN0 @@ vpn0 @@ U"00"
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when(dBus.cmd.ready){
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dBusAccess.cmd.valid := True
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dBusAccess.cmd.address := pteBuffer.PPN1(9 downto 0) @@ pteBuffer.PPN0 @@ vpn0 @@ U"00"
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when(dBusAccess.cmd.ready){
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state := State.L0_RSP
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}
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}
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is(State.L0_RSP){
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when(dBus.rsp.valid) {
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when(dBusAccess.rsp.valid) {
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state := State.IDLE
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}
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}
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}
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when(dBus.rsp.valid && (dBusRsp.leaf || dBusRsp.exception)){
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when(dBusAccess.rsp.valid && (dBusRsp.leaf || dBusRsp.exception)){
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for(port <- ports){
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when(portId === port.id) {
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port.entryToReplace.increment()
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@ -1,14 +1,14 @@
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package vexriscv.plugin
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import vexriscv.{Pipeline, Stage}
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import spinal.core.Area
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import spinal.core.{Area, Nameable}
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/**
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* Created by PIC32F_USER on 03/03/2017.
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*/
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trait Plugin[T <: Pipeline] {
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trait Plugin[T <: Pipeline] extends Nameable{
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var pipeline : T = null.asInstanceOf[T]
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def getName() = this.getClass.getSimpleName.replace("$","")
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setName(this.getClass.getSimpleName.replace("$",""))
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def setup(pipeline: T) : Unit = {}
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def build(pipeline: T) : Unit
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@ -0,0 +1,4 @@
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*.map
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*.v
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*.elf
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*.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -20,20 +20,108 @@ _start:
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csrw mtvec, x1
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csrw stvec, x1
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//Test 1
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test1: //test ram
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li x28, 1
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la x1, ROM_2
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li x2, 0x27262524
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lw x1, 4(x1)
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bne x1, x2, fail
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//Test 2
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test2: //dummy mret
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li x28, 2
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la x1, test3
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csrw mepc, x1
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li x1, 0x1800
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csrw mstatus, x1
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mret
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j fail
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test3: // jump to supervisor
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li x28, 3
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li x1, 0x0800
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csrw mstatus, x1
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la x1, test4
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csrw mepc, x1
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mret
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j fail
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test4: //test ram mmu off
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li x28, 4
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la x1, ROM_3
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li x2, 0x37363534
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lw x1, 4(x1)
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bne x1, x2, fail
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test5: //setup MMU
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li x28, 5
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la x1, MMU_TABLE_0 + 0x800
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la x2, MMU_TABLE_1
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srli x2, x2, 2
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ori x2, x2, 0x11
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sw x2, 0(x1)
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la x1, MMU_TABLE_1 + 0x000*4
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li x2, 0x80000000
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srli x2, x2, 2
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ori x2, x2, 0x1F
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sw x2, 0(x1)
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li x28, 5
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la x1, MMU_TABLE_0 + 0x900
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la x2, MMU_TABLE_2
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srli x2, x2, 2
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ori x2, x2, 0x11
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x00A*4
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la x2, ROM_4
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srli x2, x2, 2
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ori x2, x2, 0x1F
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sw x2, 0(x1)
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la x1, MMU_TABLE_0
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srli x1, x1, 12
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li x2, 0x80000000
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or x1, x1, x2
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csrw satp, x1
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test6: //read through MMU !
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li x28, 6
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li x1, 0x9000A008
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li x2, 0x4B4A4948
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lw x1, 0(x1)
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bne x1, x2, fail
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j pass
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fail: //x28 => error code
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csrwi satp, 0
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j failFence
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failFence:
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li x2, 0xF00FFF24
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sw x28, 0(x2)
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pass:
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csrwi satp, 0
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j passFence
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passFence:
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li x2, 0xF00FFF20
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sw x0, 0(x2)
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@ -45,3 +133,77 @@ pass:
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nop
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nop
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nop
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.align 12
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MMU_TABLE_0:
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.word 0
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.align 12
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MMU_TABLE_1:
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.word 0
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.align 12
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MMU_TABLE_2:
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.word 0
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.align 12
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MMU_TABLE_3:
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.word 0
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.align 12
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ROM_0:
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.word 0x03020100
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.word 0x07060504
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.word 0x0B0A0908
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.word 0x0F0E0D0C
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.align 12
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ROM_1:
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.word 0x13121110
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.word 0x17161514
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.word 0x1B1A1918
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.word 0x1F1E1D1C
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.align 12
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ROM_2:
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.word 0x23222120
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.word 0x27262524
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.word 0x2B2A2928
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.word 0x2F2E2D2C
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.align 12
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ROM_3:
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.word 0x33323130
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.word 0x37363534
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.word 0x3B3A3938
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.word 0x3F3E3D3C
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.align 12
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ROM_4:
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.word 0x43424140
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.word 0x47464544
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.word 0x4B4A4948
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.word 0x4F4E4D4C
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.align 12
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ROM_5:
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.word 0x53525150
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.word 0x57565554
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.word 0x5B5A5958
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.word 0x5F5E5D5C
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.align 12
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ROM_6:
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.word 0x63626160
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.word 0x67666564
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.word 0x6B6A6968
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.word 0x6F6E6D6C
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.align 12
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ROM_7:
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.word 0x73727170
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.word 0x77767574
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.word 0x7B7A7978
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.word 0x7F7E7D7C
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@ -1,7 +1,7 @@
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OUTPUT_ARCH( "riscv" )
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MEMORY {
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onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 8K
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onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 1M
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}
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SECTIONS
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@ -289,20 +289,42 @@ public:
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union mcause {
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uint32_t raw;
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struct {
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struct __attribute__((packed)) {
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uint32_t exceptionCode : 31;
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uint32_t interrupt : 1;
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};
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}__attribute__((packed)) mcause;
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} mcause;
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union scause {
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uint32_t raw;
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struct {
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struct __attribute__((packed)){
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uint32_t exceptionCode : 31;
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uint32_t interrupt : 1;
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};
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}__attribute__((packed)) scause;
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} scause;
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union satp {
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uint32_t raw;
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struct __attribute__((packed)){
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uint32_t ppn : 22;
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uint32_t _x : 9;
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uint32_t mode : 1;
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};
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}satp;
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union Tlb {
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uint32_t raw;
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struct __attribute__((packed)){
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uint32_t v : 1;
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uint32_t r : 1;
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uint32_t w : 1;
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uint32_t x : 1;
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uint32_t u : 1;
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uint32_t _dummy : 5;
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uint32_t ppn : 22;
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};
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};
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@ -324,6 +346,7 @@ public:
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privilege = 3;
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medeleg = 0;
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mideleg = 0;
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satp.mode = 0;
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}
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virtual void rfWrite(int32_t address, int32_t data) {
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@ -346,6 +369,29 @@ public:
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virtual bool dRead(int32_t address, int32_t size, uint32_t *data) = 0;
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virtual void dWrite(int32_t address, int32_t size, uint32_t data) = 0;
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enum AccessKind {READ,WRITE,EXECUTE};
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bool v2p(uint32_t v, uint32_t *p, AccessKind kind){
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if(privilege == 3 || satp.mode == 0){
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*p = v;
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} else {
|
||||
Tlb tlb;
|
||||
dRead((satp.ppn << 12) | ((v >> 22) << 2), 4, &tlb.raw);
|
||||
if(!tlb.v) return true;
|
||||
if(!tlb.x && !tlb.r && !tlb.w){
|
||||
dRead((tlb.ppn << 12) | (((v >> 12) & 0x3FF) << 2), 4, &tlb.raw);
|
||||
if(!tlb.v) return true;
|
||||
}
|
||||
if(!tlb.u && privilege == 0) return true;
|
||||
switch(kind){
|
||||
case READ: if(!tlb.r) return true; break;
|
||||
case WRITE: if(!tlb.w) return true; break;
|
||||
case EXECUTE: if(!tlb.x) return true; break;
|
||||
}
|
||||
*p = (tlb.ppn << 12) | (v & 0xFFF);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void exception(bool interrupt,int32_t cause) {
|
||||
exception(interrupt, cause, false, 0);
|
||||
}
|
||||
|
|
@ -396,6 +442,7 @@ public:
|
|||
|
||||
|
||||
virtual bool csrRead(int32_t csr, uint32_t *value){
|
||||
if(((csr >> 8) & 0x3) > privilege) return true;
|
||||
switch(csr){
|
||||
case MSTATUS: *value = status.raw; break;
|
||||
case MIP: *value = ip.raw; break;
|
||||
|
|
@ -415,6 +462,7 @@ public:
|
|||
case STVAL: *value = sbadaddr; break;
|
||||
case SEPC: *value = sepc; break;
|
||||
case SSCRATCH: *value = sscratch; break;
|
||||
case SATP: *value = satp.raw; break;
|
||||
default: return true; break;
|
||||
}
|
||||
return false;
|
||||
|
|
@ -422,6 +470,7 @@ public:
|
|||
|
||||
#define maskedWrite(dst, src, mask) dst=(dst & ~mask)|(src & mask);
|
||||
virtual bool csrWrite(int32_t csr, uint32_t value){
|
||||
if(((csr >> 8) & 0x3) > privilege) return true;
|
||||
switch(csr){
|
||||
case MSTATUS: status.raw = value; break;
|
||||
case MIP: ip.raw = value; break;
|
||||
|
|
@ -441,6 +490,7 @@ public:
|
|||
case STVAL: sbadaddr = value; break;
|
||||
case SEPC: sepc = value; break;
|
||||
case SSCRATCH: sscratch = value; break;
|
||||
case SATP: satp.raw = value; break;
|
||||
|
||||
default: ilegalInstruction(); return true; break;
|
||||
}
|
||||
|
|
@ -513,22 +563,26 @@ public:
|
|||
#define i16_swsp_imm ((iBits(9, 4) << 2) + (iBits(7, 2) << 6))
|
||||
uint32_t i;
|
||||
uint32_t u32Buf;
|
||||
uint32_t pAddr;
|
||||
if (pc & 2) {
|
||||
if(iRead(pc - 2, &i)){
|
||||
if(v2p(pc - 2, &pAddr, EXECUTE)){ exception(0, 12); return; }
|
||||
if(iRead(pAddr, &i)){
|
||||
exception(0, 1);
|
||||
return;
|
||||
}
|
||||
i >>= 16;
|
||||
if (i & 3 == 3) {
|
||||
uint32_t u32Buf;
|
||||
if(iRead(pc + 2, &u32Buf)){
|
||||
if(v2p(pc + 2, &pAddr, EXECUTE)){ exception(0, 12); return; }
|
||||
if(iRead(pAddr, &u32Buf)){
|
||||
exception(0, 1);
|
||||
return;
|
||||
}
|
||||
i |= u32Buf << 16;
|
||||
}
|
||||
} else {
|
||||
if(iRead(pc, &i)){
|
||||
if(v2p(pc, &pAddr, EXECUTE)){ exception(0, 12); return; }
|
||||
if(iRead(pAddr, &i)){
|
||||
exception(0, 1);
|
||||
return;
|
||||
}
|
||||
|
|
@ -561,7 +615,8 @@ public:
|
|||
if(address & (size-1)){
|
||||
exception(0, 4, address);
|
||||
} else {
|
||||
if(dRead(address, size, &data)){
|
||||
if(v2p(address, &pAddr, READ)){ exception(0, 13); return; }
|
||||
if(dRead(pAddr, size, &data)){
|
||||
exception(0, 5, address);
|
||||
} else {
|
||||
switch ((i >> 12) & 0x7) {
|
||||
|
|
@ -580,7 +635,8 @@ public:
|
|||
if(address & (size-1)){
|
||||
exception(0, 6, address);
|
||||
} else {
|
||||
dWrite(address, size, i32_rs2);
|
||||
if(v2p(address, &pAddr, WRITE)){ exception(0, 15); return; }
|
||||
dWrite(pAddr, size, i32_rs2);
|
||||
pcWrite(pc + 4);
|
||||
}
|
||||
}break;
|
||||
|
|
@ -645,18 +701,18 @@ public:
|
|||
switch(i){
|
||||
case 0x30200073:{ //MRET
|
||||
if(privilege < 3){ ilegalInstruction(); return;}
|
||||
status.mpp = 0;
|
||||
privilege = status.mpp;
|
||||
status.mie = status.mpie;
|
||||
status.mpie = 1;
|
||||
privilege = status.mpp;
|
||||
status.mpp = 0;
|
||||
pcWrite(mepc);
|
||||
}break;
|
||||
case 0x10200073:{ //SRET
|
||||
if(privilege < 1){ ilegalInstruction(); return;}
|
||||
status.spp = 0;
|
||||
privilege = status.spp;
|
||||
status.sie = status.spie;
|
||||
status.spie = 1;
|
||||
privilege = status.spp;
|
||||
status.spp = 0;
|
||||
pcWrite(sepc);
|
||||
}break;
|
||||
case 0x00000073:{ //ECALL
|
||||
|
|
@ -699,7 +755,8 @@ public:
|
|||
if(address & 0x3){
|
||||
exception(0, 4, address);
|
||||
} else {
|
||||
if(dRead(i16_rf1 + i16_lw_imm, 4, &data)) {
|
||||
if(v2p(address, &pAddr, READ)){ exception(0, 13); return; }
|
||||
if(dRead(address, 4, &data)) {
|
||||
exception(1, 5, address);
|
||||
} else {
|
||||
rfWrite(i16_addr2, data); pcWrite(pc + 2);
|
||||
|
|
@ -711,7 +768,8 @@ public:
|
|||
if(address & 0x3){
|
||||
exception(0, 6, address);
|
||||
} else {
|
||||
dWrite(address, 4, i16_rf2);
|
||||
if(v2p(address, &pAddr, WRITE)){ exception(0, 15); return; }
|
||||
dWrite(pAddr, 4, i16_rf2);
|
||||
pcWrite(pc + 2);
|
||||
}
|
||||
}break;
|
||||
|
|
@ -746,7 +804,8 @@ public:
|
|||
if(address & 0x3){
|
||||
exception(0, 4, address);
|
||||
} else {
|
||||
if(dRead(address, 4, &data)){
|
||||
if(v2p(address, &pAddr, READ)){ exception(0, 13); return; }
|
||||
if(dRead(pAddr, 4, &data)){
|
||||
exception(1, 5, address);
|
||||
} else {
|
||||
rfWrite(rd32, data); pcWrite(pc + 2);
|
||||
|
|
@ -775,7 +834,8 @@ public:
|
|||
if(address & 3){
|
||||
exception(0,6, address);
|
||||
} else {
|
||||
dWrite(address, 4, regs[iBits(2,5)]); pcWrite(pc + 2);
|
||||
if(v2p(address, &pAddr, WRITE)){ exception(0, 15); return; }
|
||||
dWrite(pAddr, 4, regs[iBits(2,5)]); pcWrite(pc + 2);
|
||||
}
|
||||
}break;
|
||||
}
|
||||
|
|
@ -884,7 +944,8 @@ public:
|
|||
cout << "dRead size=" << size << endl;
|
||||
fail();
|
||||
}
|
||||
if(address & (size-1) != 0) cout << "Ref did a unaligned read" << endl;
|
||||
if(address & (size-1) != 0)
|
||||
cout << "Ref did a unaligned read" << endl;
|
||||
if((address & 0xF0000000) == 0xF0000000){
|
||||
MemRead t = periphRead.front();
|
||||
if(t.address != address || t.size != size){
|
||||
|
|
@ -899,7 +960,8 @@ public:
|
|||
return false;
|
||||
}
|
||||
virtual void dWrite(int32_t address, int32_t size, uint32_t data){
|
||||
if(address & (size-1) != 0) cout << "Ref did a unaligned write" << endl;
|
||||
if(address & (size-1) != 0)
|
||||
cout << "Ref did a unaligned write" << endl;
|
||||
if((address & 0xF0000000) == 0xF0000000){
|
||||
MemWrite w;
|
||||
w.address = address;
|
||||
|
|
@ -2879,6 +2941,10 @@ int main(int argc, char **argv, char **env) {
|
|||
printf("BOOT\n");
|
||||
timespec startedAt = timer_start();
|
||||
|
||||
#ifdef MMU
|
||||
redo(REDO,Workspace("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
#endif
|
||||
return 0;
|
||||
|
||||
for(int idx = 0;idx < 1;idx++){
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
DEBUG?=no
|
||||
DEBUG?=yes
|
||||
|
||||
IBUS?=CACHED
|
||||
IBUS_TC?=no
|
||||
|
|
|
|||
Loading…
Reference in New Issue