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RV32IC is passing some of the compressed Riscv-test tests

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This commit is contained in:
Dolu1990 2018-03-21 20:30:09 +01:00
parent f872d599e2
commit af638e7bde
13 changed files with 5854 additions and 20 deletions
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5
src/main/scala/vexriscv/Pipeline.scala
View file

@ -7,12 +7,14 @@ import spinal.lib._
import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer
trait PipelineConfig[T]
trait Pipeline {
type T <: Pipeline
val plugins = ArrayBuffer[Plugin[T]]()
var stages = ArrayBuffer[Stage]()
var unremovableStages = mutable.Set[Stage]()
val configs = mutable.HashMap[PipelineConfig[_], Any]()
// val services = ArrayBuffer[Any]()
def indexOf(stage : Stage) = stages.indexOf(stage)
@ -28,6 +30,9 @@ trait Pipeline {
filtered.length != 0
}
def update[T](that : PipelineConfig[T], value : T) : Unit = configs(that) = value
def apply[T](that : PipelineConfig[T]) : T = configs(that).asInstanceOf[T]
def build(): Unit ={
plugins.foreach(_.pipeline = this.asInstanceOf[T])
plugins.foreach(_.setup(this.asInstanceOf[T]))

7
src/main/scala/vexriscv/VexRiscv.scala
View file

@ -5,7 +5,9 @@ import spinal.core._
case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
//Default Stageables
object IS_RVC extends Stageable(Bool)
object BYPASSABLE_EXECUTE_STAGE extends Stageable(Bool)
object BYPASSABLE_MEMORY_STAGE extends Stageable(Bool)
object RS1 extends Stageable(Bits(32 bits))
@ -43,7 +45,7 @@ case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
object Src1CtrlEnum extends SpinalEnum(binarySequential){
val RS, IMU, FOUR = newElement() //IMU, IMZ IMJB
val RS, IMU, PC_INCREMENT = newElement() //IMU, IMZ IMJB
}
object Src2CtrlEnum extends SpinalEnum(binarySequential){
@ -55,6 +57,7 @@ case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
object RVC_GEN extends PipelineConfig[Boolean]
class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
type T = VexRiscv
import config._
@ -76,6 +79,8 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
decode.arbitration.removeIt.noBackendCombMerge //Verilator perf
memory.arbitration.removeIt.noBackendCombMerge
execute.arbitration.flushAll.noBackendCombMerge
this(RVC_GEN) = false
}

4
src/main/scala/vexriscv/plugin/BranchPlugin.scala
View file

@ -45,7 +45,7 @@ class BranchPlugin(earlyBranch : Boolean,
)
val jActions = List[(Stageable[_ <: BaseType],Any)](
SRC1_CTRL -> Src1CtrlEnum.FOUR,
SRC1_CTRL -> Src1CtrlEnum.PC_INCREMENT,
SRC2_CTRL -> Src2CtrlEnum.PC,
SRC_USE_SUB_LESS -> False,
REGFILE_WRITE_VALID -> True
@ -139,7 +139,7 @@ class BranchPlugin(earlyBranch : Boolean,
}
if(catchAddressMisaligned) { //TODO conflict with instruction cache two stage
branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && (if(pipeline(RVC_GEN)) jumpInterface.payload(0 downto 0) =/= 0 else jumpInterface.payload(1 downto 0) =/= 0)
branchExceptionPort.code := 0
branchExceptionPort.badAddr := jumpInterface.payload
}

2
src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
View file

@ -278,6 +278,8 @@ object SymplifyBit{
}
def getPrimeImplicantsByTrue(trueTerms: Seq[Masked], inputWidth : Int) : Seq[Masked] = getPrimeImplicantsByTrueAndDontCare(trueTerms, Nil, inputWidth)
// Return primes implicants for the trueTerms, default value is False.
// You can insert don't care values by adding non-prime implicants in the trueTerms
// Will simplify the trueTerms from the most constrained ones to the least constrained ones

157
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View file

@ -155,6 +155,94 @@ trait IBusFetcher{
def nextPc() : (Bool, UInt)
}
object RvcDecompressor{
def main(args: Array[String]): Unit = {
SpinalVerilog(new Component{
Delay(out(apply(Delay(in Bits(16 bits),2))),2)
}.setDefinitionName("Decompressor"))
}
def apply(i : Bits): Bits ={
val ret = Bits(32 bits).assignDontCare()
val rch = B"01" ## i(9 downto 7)
val rcl = B"01" ## i(4 downto 2)
val addi5spnImm = B"00" ## i(10 downto 7) ## i(12 downto 11) ## i(5) ## i(6) ## B"00"
val lwImm = B"00000" ## i(5) ## i(12 downto 10) ## i(6) ## B"00"
def swImm = lwImm
val addImm = B((11 downto 5) -> i(12), (4 downto 0) -> i(6 downto 2))
def lImm = addImm
val jalImm = B((9 downto 0) -> i(12)) ## i(8) ## i(10 downto 9) ## i(6) ## i(7) ## i(2) ## i(11) ## i(5 downto 3) ## B"0"
val luiImm = B((14 downto 0) -> i(12)) ## i(6 downto 2) ## B"0000_0000_0000"
val shiftImm = i(6 downto 2)
val addi16spImm = B((2 downto 0) -> i(12)) ## i(4 downto 3) ## i(5) ## i(2) ## i(6) ## B"0000"
val jImm = B((9 downto 0) -> i(12)) ## i(8) ## i(10 downto 9) ## i(6) ## i(7) ## i(2) ## i(11) ## i(5 downto 3) ## B"0"
val bImm = B((4 downto 0) -> i(12)) ## i(6 downto 5) ## i(2) ## i(11 downto 10) ## i(4 downto 3) ## B"0"
def lwspImm = B"0000" ## i(3 downto 2) ## i(12) ## i(6 downto 4) ## B"00"
def swspImm = B"0000" ## i(8 downto 7) ## i(12 downto 9) ## B"00"
val x0 = B"00000"
val x1 = B"00001"
val x2 = B"00010"
switch(i(1 downto 0) ## i(15 downto 13)){
is(0){ret := addi5spnImm ## B"00010" ## B"000" ## rcl ## B"0010011"} //C.ADDI4SPN -> addi rd0, x2, nzuimm[9:2].
is(2){ret := lwImm ## rch ## B"010" ## rcl ## B"0000011"} //C.LW -> lw rd', offset[6:2](rs1')
is(6){ret := swImm(11 downto 5) ## rcl ## rch ## B"010" ## swImm(4 downto 0) ## B"0100011"} //C.SW -> sw rs2',offset[6:2](rs1')
is(8){ret := addImm ## i(11 downto 7) ## B"000" ## i(11 downto 7) ## B"0010011"} //C.ADDI -> addi rd, rd, nzimm[5:0].
is(9){ret := jalImm(20) ## jalImm(10 downto 1) ## jalImm(11) ## jalImm(19 downto 12) ## x1 ## B"1101111"} //C.JAL -> jalr x1, rs1, 0.
is(10){ret := lImm ## B"00000" ## B"000" ## i(11 downto 7) ## B"0010011"} //C.LI -> addi rd, x0, imm[5:0].
is(11){ //C.ADDI16SP C.LUI ->
val addi16sp = addi16spImm ## i(11 downto 7) ## B"000" ## i(11 downto 7) ## B"0010011"
val lui = luiImm(31 downto 12) ## i(11 downto 7) ## B"0110111"
ret := (i(11 downto 7) === 2) ? addi16sp | lui
}
is(12){
val isImmediate = i(11 downto 10) =/= "11"
val isShift = !i(11)
val func3 = i(11 downto 10).mux(
0 -> B"101",
1 -> B"101",
2 -> B"111",
3 -> i(6 downto 5).mux(
0 -> B"000",
1 -> B"100",
2 -> B"110",
3 -> B"111"
)
)
val msbs = Mux(
sel = i(11 downto 10) === "10",
whenTrue = B((6 downto 0) -> i(12)), //andi
whenFalse = B"0" ## (i(11 downto 10) === B"01" || (i(11 downto 10) === B"11" && i(6 downto 5) === B"00")) ## B"00000"
)
val rs2Shift = isShift ? shiftImm | rcl
val opc = (isImmediate ? B"0010011" | B"0110011")
ret := msbs ## rs2Shift ## rch ## func3 ## rch ## opc
}
is(13){ ret := jImm(20) ## jImm(10 downto 1) ## jImm(11) ## jImm(19 downto 12) ## x0 ## B"1101111"}
is(14){ ret := bImm(12) ## bImm(10 downto 5) ## x0 ## rch ## B"000" ## bImm(4 downto 1) ## bImm(11) ## B"1100011" }
is(15){ ret := bImm(12) ## bImm(10 downto 5) ## x0 ## rch ## B"001" ## bImm(4 downto 1) ## bImm(11) ## B"1100011" }
is(16){ ret := B"0000000" ## i(6 downto 2) ## i(11 downto 7) ## B"001" ## i(11 downto 7) ## B"0010011" }
is(18){ ret := lwspImm ## x2 ## B"010" ## i(11 downto 7) ## B"0000011" }
is(20) {
val add = B"000_0000" ## i(6 downto 2) ## (i(12) ? i(11 downto 7) | x0) ## B"000" ## i(11 downto 7) ## B"0110011" //add => add rd, rd, rs2 mv => add rd, x0, rs2
val j = B"0000_0000_0000" ## i(11 downto 7) ## B"000" ## (i(12) ? x1 | x0) ## B"1100111" //jr => jalr x0, rs1, 0. jalr => jalr x1, rs1, 0.
val ebreak = B"000000000001_00000_000_00000_1110011" //EBREAK
val addJ = (i(6 downto 2) === 0) ? j | add
ret := (i(12 downto 2) === B"100_0000_0000") ? ebreak | addJ
}
is(22){ ret := swspImm(11 downto 5) ## i(6 downto 2) ## x2 ## B"010" ## swImm(4 downto 0) ## B"0100011" }
}
ret
}
}
class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean, pendingMax : Int = 7) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
var iBus : IBusSimpleBus = null
var prefetchExceptionPort : Flow[ExceptionCause] = null
@ -162,6 +250,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
def keepPcPlus4 = false
def decodePcGen = true
def compressedGen = true
assert(!(compressedGen && !decodePcGen))
lazy val fetcherHalt = False
lazy val decodeNextPcValid = Bool
lazy val decodeNextPc = UInt(32 bits)
@ -185,6 +274,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
val exceptionService = pipeline.service(classOf[ExceptionService])
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1).setName("iBusErrorExceptionnPort")
}
pipeline(RVC_GEN) = compressedGen
}
override def build(pipeline: VexRiscv): Unit = {
@ -221,12 +312,20 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
pcReg := pcPlus4
}
//Realign
if(compressedGen){
when(output.fire){
pcReg(1 downto 0) := 0
}
}
//application of the selected jump request
when(jump.pcLoad.valid) {
pcReg := jump.pcLoad.payload
}
output.valid := (RegNext(True) init (False)) // && !jump.pcLoad.valid
output.payload := pcReg
}
@ -234,10 +333,14 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
val decodePc = ifGen(decodePcGen)(new Area {
//PC calculation without Jump
val pcReg = Reg(UInt(32 bits)) init (resetVector) addAttribute (Verilator.public)
val pcPlus4 = pcReg + 4
if (keepPcPlus4) KeepAttribute(pcPlus4)
val pcPlus = if(compressedGen)
pcReg + ((decode.input(IS_RVC)) ? U(2) | U(4))
else
pcReg + 4
if (keepPcPlus4) KeepAttribute(pcPlus)
when(decode.arbitration.isFiring) {
pcReg := pcPlus4
pcReg := pcPlus
}
//application of the selected jump request
@ -258,9 +361,16 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
pendingCmd := pendingCmdNext
iBus.cmd.valid := input.valid && output.ready && pendingCmd =/= pendingMax
iBus.cmd.pc := input.payload
iBus.cmd.pc := input.payload(31 downto 2) @@ "00"
}
case class FetchRsp() extends Bundle {
val pc = UInt(32 bits)
val rsp = IBusSimpleRsp()
val isRvc = Bool
}
val iBusRsp = new Area {
val input = iBusCmd.output.m2sPipe(flush)// ASYNC .throwWhen(flush)
@ -273,10 +383,6 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
val rsp = iBus.rsp.throwWhen(discardCounter =/= 0).toStream.s2mPipe(flush)
case class FetchRsp() extends Bundle {
val pc = UInt(32 bits)
val rsp = IBusSimpleRsp()
}
val fetchRsp = FetchRsp()
fetchRsp.pc := input.payload
@ -285,12 +391,42 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
val output = StreamJoin(Seq(input, rsp), fetchRsp)
}
val decompressor = ifGen(decodePcGen)(new Area{
def input = iBusRsp.output
val output = Stream(FetchRsp())
val bufferValid = RegInit(False)
val bufferData = Reg(Bits(16 bits))
val raw = Mux(
sel = bufferValid,
whenTrue = input.rsp.inst(15 downto 0) ## bufferData,
whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
)
val isRvc = raw(1 downto 0) =/= 3
val decompressed = RvcDecompressor(raw(15 downto 0))
output.valid := isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1)))
output.pc := input.pc
output.isRvc := isRvc
output.rsp.inst := isRvc ? decompressed | raw
output.rsp.error := False
input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready))
bufferValid clearWhen(output.fire)
when(input.ready){
when(input.valid) {
bufferValid := !(!isRvc && !input.pc(1) && !bufferValid)
}
bufferData := input.rsp.inst(31 downto 16)
}
bufferValid.clearWhen(flush)
})
val injector = new Area {
val inputBeforeHalt = iBusRsp.output//.s2mPipe(flush)
val inputBeforeHalt = if(decodePcGen) decompressor.output else iBusRsp.output//.s2mPipe(flush)
val input = inputBeforeHalt.haltWhen(fetcherHalt)
val stage = input.m2sPipe(flush || decode.arbitration.isRemoved)
@ -308,6 +444,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
decode.insert(INSTRUCTION) := stage.rsp.inst
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), input.rsp.inst)
decode.insert(INSTRUCTION_READY) := True
if(compressedGen) decode.insert(IS_RVC) := stage.isRvc
if(catchAccessFault){
decodeExceptionPort.valid := decode.arbitration.isValid && stage.rsp.error

4
src/main/scala/vexriscv/plugin/SrcPlugin.scala
View file

@ -1,6 +1,6 @@
package vexriscv.plugin
import vexriscv.{Riscv, VexRiscv}
import vexriscv.{RVC_GEN, Riscv, VexRiscv}
import spinal.core._
@ -15,7 +15,7 @@ class SrcPlugin(separatedAddSub : Boolean, executeInsertion : Boolean = false) e
val imm = Riscv.IMM(input(INSTRUCTION))
insert(SRC1) := input(SRC1_CTRL).mux(
Src1CtrlEnum.RS -> output(RS1),
Src1CtrlEnum.FOUR -> B(4),
Src1CtrlEnum.PC_INCREMENT -> (if(pipeline(RVC_GEN)) Mux(input(IS_RVC), B(2), B(4)) else B(4)).resized,
Src1CtrlEnum.IMU -> imm.u.resized
)
insert(SRC2) := input(SRC2_CTRL).mux(

8
src/test/cpp/custom/simd_add/build/custom_simd_add.map
View file

@ -8,12 +8,12 @@ onChipRam 0x0000000000000000 0x0000000000002000 w !xr
Linker script and memory map
LOAD build/src/crt.o
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/rv32i/ilp32/libgcc.a
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a
START GROUP
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
END GROUP
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/rv32i/ilp32/libgcc.a
LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a
0x0000000000000000 . = 0x0
.crt_section 0x0000000000000000 0xd0

12
src/test/cpp/regression/main.cpp
View file

@ -386,7 +386,10 @@ public:
#ifdef REF
if(bootPc != -1) top->VexRiscv->core->prefetch_pc = bootPc;
#else
if(bootPc != -1) top->VexRiscv->IBusSimplePlugin_pcCalc_pcReg = bootPc;
if(bootPc != -1) {
top->VexRiscv->IBusSimplePlugin_fetchPc_pcReg = bootPc;
top->VexRiscv->IBusSimplePlugin_decodePc_pcReg = bootPc;
}
#endif
@ -451,6 +454,7 @@ public:
for(SimElement* simElement : simElements) simElement->preCycle();
#ifndef COMPRESSED
if(withInstructionReadCheck){
if(top->VexRiscv->decode_arbitration_isValid && !top->VexRiscv->decode_arbitration_haltItself && !top->VexRiscv->decode_arbitration_flushAll){
uint32_t expectedData;
@ -459,6 +463,7 @@ public:
assertEq(top->VexRiscv->decode_INSTRUCTION,expectedData);
}
}
#endif
checks();
//top->eval();
@ -1719,6 +1724,7 @@ int main(int argc, char **argv, char **env) {
for(const string &name : riscvTestMemory){
redo(REDO,RiscvTest(name).run();)
}
#ifdef MUL
for(const string &name : riscvTestMul){
redo(REDO,RiscvTest(name).run();)
@ -1730,6 +1736,10 @@ int main(int argc, char **argv, char **env) {
}
#endif
#ifdef COMPRESSED
redo(REDO,RiscvTest("rv32uc-p-rvc").bootAt(0x800000FCu)->run());
#endif
#ifdef CSR
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };

5
src/test/cpp/regression/makefile
View file

@ -22,6 +22,7 @@ TRACE_WITH_TIME=no
REF_TIME=no
THREAD_COUNT?=4
MTIME_INSTR_FACTOR?=no
COMPRESSED?=no
ADDCFLAGS += -CFLAGS -DIBUS_${IBUS}
@ -31,6 +32,10 @@ ADDCFLAGS += -CFLAGS -pthread
ADDCFLAGS += -CFLAGS -DTHREAD_COUNT=${THREAD_COUNT}
ifeq ($(COMPRESSED),yes)
ADDCFLAGS += -CFLAGS -DCOMPRESSED
endif
ifeq ($(DHRYSTONE),yes)
ADDCFLAGS += -CFLAGS -DDHRYSTONE
endif

1
src/test/python/tool/disasm.s Normal file
View file

@ -0,0 +1 @@
.word 0xf47413

11
src/test/python/tool/hexToAsm.py Executable file
View file

@ -0,0 +1,11 @@
#!/usr/bin/env python3
from os import system
from sys import argv
with open("disasm.s", "w") as f:
instr = int(argv[1], 16)
print(".word 0x%04x" % (instr), file=f)
system("riscv64-unknown-elf-gcc -c disasm.s")
system("riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o")

4904
src/test/resources/asm/rv32uc-p-rvc.dump Normal file
View file

File diff suppressed because it is too large Load diff

754
src/test/resources/hex/rv32uc-p-rvc.hex Normal file
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@ -0,0 +1,754 @@
:0200000480007A
:100000006F00C004732F2034930F8000630AFF0336
:10001000930F90006306FF03930FB0006302FF038A
:10002000170F0080130F0FFE63040F0067000F000F
:10003000732F203463540F006F00400093E19153FD
:10004000173F000023203FFC6FF09FFF732540F116
:1000500063100500970200009382020173905230F2
:1000600073500018970200009382C20173905230BF
:100070009302F0FF7390023B9302F0017390023AF7
:1000800097020000938282017390523073502030A7
:1000900073503030735040309301000097020000DD
:1000A000938282F673905230130510001315F501F8
:1000B000634805000F00F00F93011000730000006B
:1000C00097020080938202F4638E020073905210B4
:1000D000B7B20000938292107390223073232030C5
:1000E000E39E62F473500030970200009382420155
:1000F00073901234732540F1730020309301200077
:100100009305A0296F10B06F1032547698BADCFEB8
:100110001032547698BADCFE130000001300000081
:100120001300000013000000130000001300000083
:100130001300000013000000130000001300000073
:100140001300000013000000130000001300000063
:100150001300000013000000130000001300000053
:100160001300000013000000130000001300000043
:100170001300000013000000130000001300000033
:100180001300000013000000130000001300000023
:100190001300000013000000130000001300000013
:1001A0001300000013000000130000001300000003
:1001B00013000000130000001300000013000000F3
:1001C00013000000130000001300000013000000E3
:1001D00013000000130000001300000013000000D3
:1001E00013000000130000001300000013000000C3
:1001F00013000000130000001300000013000000B3
:1002000013000000130000001300000013000000A2
:100210001300000013000000130000001300000092
:100220001300000013000000130000001300000082
:100230001300000013000000130000001300000072
:100240001300000013000000130000001300000062
:100250001300000013000000130000001300000052
:100260001300000013000000130000001300000042
:100270001300000013000000130000001300000032
:100280001300000013000000130000001300000022
:100290001300000013000000130000001300000012
:1002A0001300000013000000130000001300000002
:1002B00013000000130000001300000013000000F2
:1002C00013000000130000001300000013000000E2
:1002D00013000000130000001300000013000000D2
:1002E00013000000130000001300000013000000C2
:1002F00013000000130000001300000013000000B2
:1003000013000000130000001300000013000000A1
:100310001300000013000000130000001300000091
:100320001300000013000000130000001300000081
:100330001300000013000000130000001300000071
:100340001300000013000000130000001300000061
:100350001300000013000000130000001300000051
:100360001300000013000000130000001300000041
:100370001300000013000000130000001300000031
:100380001300000013000000130000001300000021
:100390001300000013000000130000001300000011
:1003A0001300000013000000130000001300000001
:1003B00013000000130000001300000013000000F1
:1003C00013000000130000001300000013000000E1
:1003D00013000000130000001300000013000000D1
:1003E00013000000130000001300000013000000C1
:1003F00013000000130000001300000013000000B1
:1004000013000000130000001300000013000000A0
:100410001300000013000000130000001300000090
:100420001300000013000000130000001300000080
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