Improve d$ coupled timings
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5493c55ab0
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@ -52,7 +52,8 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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dBusCmdSlavePipe : Boolean = false,
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dBusRspSlavePipe : Boolean = false,
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relaxedMemoryTranslationRegister : Boolean = false,
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csrInfo : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService with DBusEncodingService with VexRiscvRegressionArg {
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csrInfo : Boolean = false,
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tightlyCoupledAddressStage : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService with DBusEncodingService with VexRiscvRegressionArg {
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import config._
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assert(!(config.withExternalAmo && !dBusRspSlavePipe))
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assert(isPow2(cacheSize))
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@ -405,6 +406,14 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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}
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if(tightlyGen){
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tightlyCoupledAddressStage match {
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case false =>
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case true => {
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val go = RegInit(False) setWhen(arbitration.isValid) clearWhen(arbitration.isMoving)
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arbitration.haltItself.setWhen(arbitration.isValid && input(MEMORY_TIGHTLY).orR && !go)
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}
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}
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insert(MEMORY_TIGHTLY) := B(tightlyCoupledPorts.map(_.p.hit(input(SRC_ADD).asUInt)))
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when(insert(MEMORY_TIGHTLY).orR){
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cache.io.cpu.execute.isValid := False
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@ -412,7 +421,8 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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}
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for((port, sel) <- (tightlyCoupledPorts, input(MEMORY_TIGHTLY).asBools).zipped){
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port.bus.enable := arbitration.isValid && input(MEMORY_ENABLE) && sel && !arbitration.isStuck
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port.bus.address := input(SRC_ADD).asUInt.resized
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port.bus.address := Delay(input(SRC_ADD), tightlyCoupledAddressStage.toInt).asUInt.resized
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port.bus.write_enable := input(MEMORY_WR)
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port.bus.write_data := input(MEMORY_STORE_DATA_RF)
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port.bus.write_mask := size.mux (
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@ -446,7 +456,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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input(HAS_SIDE_EFFECT) := False
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}
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insert(MEMORY_TIGHTLY_DATA) := OhMux(input(MEMORY_TIGHTLY), tightlyCoupledPorts.map(_.bus.read_data))
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}
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KeepAttribute(insert(MEMORY_TIGHTLY_DATA)) }
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}
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val managementStage = stages.last
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