Add AhbLite3 simulation config
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Dolu1990
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package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.avalon.AvalonMM
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import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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/**
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* Created by spinalvm on 14.07.17.
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*/
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//class VexRiscvAvalon(debugClockDomain : ClockDomain) extends Component{
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//
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//}
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//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON
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object VexRiscvAhbLite3ForSim{
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def main(args: Array[String]) {
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val report = SpinalVerilog{
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//CPU configuration
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val cpuConfig = VexRiscvConfig(
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plugins = List(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = true,
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prediction = STATIC,
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catchAccessFault = false,
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compressedGen = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine =32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = true,
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// catchAccessFault = true,
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// catchMemoryTranslationMiss = true,
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// asyncTagMemory = false,
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// twoCycleRam = true
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// )
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// // askMemoryTranslation = true,
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// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// // portTlbSize = 4
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// // )
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// ),
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// new DBusCachedPlugin(
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// config = new DataCacheConfig(
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// cacheSize = 4096,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessError = true,
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// catchIllegal = true,
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// catchUnaligned = true,
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// catchMemoryTranslationMiss = true
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// ),
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// memoryTranslatorPortConfig = null
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// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// // portTlbSize = 6
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// // )
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// ),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrelShifterPlugin,
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new MulPlugin,
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new DivPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true
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),
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new CsrPlugin(
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config = CsrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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mimpid = null,
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mhartid = null,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.NONE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ecallGen = false,
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wfiGenAsWait = false,
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ucycleAccess = CsrAccess.NONE
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)
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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//CPU instanciation
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val cpu = new VexRiscv(cpuConfig)
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//CPU modifications to be an AhbLite3 one
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cpu.rework {
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for (plugin <- cpuConfig.plugins) plugin match {
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case plugin: IBusSimplePlugin => {
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plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
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master(plugin.iBus.toAhbLite3Master()).setName("iBusAhbLite3")
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}
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// case plugin: DBusSimplePlugin => {
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// plugin.dBus.setAsDirectionLess()
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// master(plugin.dBus.toAhbLite3Master()).setName("dBusAhbLite3")
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// }
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// case plugin: IBusCachedPlugin => {
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// plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
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// iBus = master(plugin.iBus.toAvalon())
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// .setName("iBusAvalon")
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// .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
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// }
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// case plugin: DBusCachedPlugin => {
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// plugin.dBus.setAsDirectionLess()
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// master(plugin.dBus.toAvalon())
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// .setName("dBusAvalon")
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// .addTag(ClockDomainTag(ClockDomain.current))
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// }
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// case plugin: DebugPlugin => plugin.debugClockDomain {
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// plugin.io.bus.setAsDirectionLess()
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// slave(plugin.io.bus.fromAvalon())
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// .setName("debugBusAvalon")
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// .addTag(ClockDomainTag(plugin.debugClockDomain))
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// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
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// plugin.io.resetOut
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// .addTag(ResetEmitterTag(plugin.debugClockDomain))
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// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit
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// }
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case _ =>
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}
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}
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cpu
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}
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}
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}
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