SmpCluster now with proper jtag and plic
This commit is contained in:
Dolu1990
parent
2e8a059c77
commit
b0cd88c462
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@ -6,8 +6,10 @@ import spinal.core.sim.{onSimEnd, simSuccess}
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import spinal.lib._
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import spinal.lib.bus.bmb.sim.BmbMemoryAgent
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import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
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import spinal.lib.com.jtag.sim.JtagTcp
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import spinal.lib.system.debugger.SystemDebuggerConfig
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
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@ -38,21 +40,23 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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val externalInterrupts = in Bits(p.cpuConfigs.size bits)
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val softwareInterrupts = in Bits(p.cpuConfigs.size bits)
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val externalSupervisorInterrupts = in Bits(p.cpuConfigs.size bits)
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val jtag = slave(Jtag())
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val debugBus = slave(Bmb(SystemDebuggerConfig().getBmbParameter.copy(addressWidth = 20)))
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val debugReset = out Bool()
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val time = in UInt(64 bits)
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}
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io.debugReset := False
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val cpus = for((cpuConfig, cpuId) <- p.cpuConfigs.zipWithIndex) yield new Area{
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var iBus : Bmb = null
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var dBus : Bmb = null
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var debug : Bmb = null
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cpuConfig.plugins.foreach {
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case plugin: DebugPlugin => debugClockDomain{
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plugin.debugClockDomain = debugClockDomain
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}
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case _ =>
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}
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if(cpuId == 0) cpuConfig.plugins += new DebugPlugin(debugClockDomain)
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cpuConfig.plugins += new DebugPlugin(debugClockDomain)
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val core = new VexRiscv(cpuConfig)
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core.plugins.foreach {
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case plugin: IBusCachedPlugin => iBus = plugin.iBus.toBmb()
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@ -65,8 +69,8 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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if (plugin.utime != null) plugin.utime := io.time
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}
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case plugin: DebugPlugin => debugClockDomain{
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io.debugReset := RegNext(plugin.io.resetOut)
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io.jtag <> plugin.io.bus.fromJtag()
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io.debugReset setWhen(RegNext(plugin.io.resetOut))
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debug = plugin.io.bus.fromBmb()
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}
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case _ =>
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}
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@ -97,19 +101,18 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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io.dMem << invalidateMonitor.io.output
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// val iBusArbiter = BmbArbiter(
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// p = iBusArbiterParameter,
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// portCount = cpus.size,
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// pendingRspMax = 64,
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// lowerFirstPriority = false,
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// inputsWithInv = cpus.map(_ => true),
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// inputsWithSync = cpus.map(_ => true),
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// pendingInvMax = 16
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// )
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//
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// (iBusArbiter.io.inputs, cpus).zipped.foreach(_ << _.iBus)
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// io.iMem << iBusArbiter.io.output
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(io.iMems, cpus).zipped.foreach(_ << _.iBus)
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val debug = debugClockDomain on new Area{
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val arbiter = BmbDecoder(
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p = io.debugBus.p,
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mappings = List.tabulate(p.cpuConfigs.size)(i => SizeMapping(0x00000 + i*0x1000, 0x1000)),
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capabilities = List.fill(p.cpuConfigs.size)(io.debugBus.p),
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pendingMax = 2
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)
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arbiter.io.input << io.debugBus
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(arbiter.io.outputs, cpus.map(_.debug)).zipped.foreach(_ >> _)
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}
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}
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@ -417,10 +420,7 @@ object VexRiscvSmpClusterTestInfrastructure{
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import spinal.core.sim._
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dut.clockDomain.forkStimulus(10)
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dut.debugClockDomain.forkStimulus(10)
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// JtagTcp(dut.io.jtag, 100)
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dut.io.jtag.tck #= false
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dut.io.jtag.tdi #= false
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dut.io.jtag.tms #= false
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dut.io.debugBus.cmd.valid #= false
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}
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}
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@ -3,13 +3,15 @@ package vexriscv.demo.smp
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import spinal.core._
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import spinal.lib.bus.bmb._
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.{Jtag, JtagTapInstructionCtrl}
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import spinal.lib._
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import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
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import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
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import spinal.lib.eda.bench.Bench
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import spinal.lib.misc.Clint
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import spinal.lib.misc.plic.{PlicGatewayActiveHigh, PlicMapper, PlicMapping, PlicTarget}
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import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
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import spinal.lib.system.debugger.{JtagBridgeNoTap, SystemDebugger, SystemDebuggerConfig}
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import vexriscv.demo.smp.VexRiscvLitexSmpClusterOpenSbi.{cpuCount, parameter}
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import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
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import vexriscv.{VexRiscv, VexRiscvConfig}
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@ -25,7 +27,8 @@ case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParamet
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//addAttribute("""mark_debug = "true"""")
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case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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debugClockDomain : ClockDomain) extends Component{
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debugClockDomain : ClockDomain,
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jtagClockDomain : ClockDomain) extends Component{
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val peripheralWishboneConfig = WishboneConfig(
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addressWidth = 30,
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@ -41,9 +44,9 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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val iMem = master(LiteDramNative(p.liteDram))
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val peripheral = master(Wishbone(peripheralWishboneConfig))
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val clint = slave(Wishbone(Clint.getWisboneConfig()))
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val externalInterrupts = in Bits(p.cluster.cpuConfigs.size bits)
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val externalSupervisorInterrupts = in Bits(p.cluster.cpuConfigs.size bits)
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val jtag = slave(Jtag())
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val plic = slave(Wishbone(WishboneConfig(addressWidth = 20, dataWidth = 32)))
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val interrupts = in Bits(32 bits)
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val jtagInstruction = slave(JtagTapInstructionCtrl())
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val debugReset = out Bool()
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}
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val cpuCount = p.cluster.cpuConfigs.size
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@ -51,14 +54,25 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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clint.driveFrom(WishboneSlaveFactory(io.clint))
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val cluster = VexRiscvSmpCluster(p.cluster, debugClockDomain)
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cluster.io.externalInterrupts <> io.externalInterrupts
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cluster.io.externalSupervisorInterrupts <> io.externalSupervisorInterrupts
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cluster.io.jtag <> io.jtag
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cluster.io.debugReset <> io.debugReset
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cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
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cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
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cluster.io.time := clint.time
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val debug = debugClockDomain on new Area{
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val jtagConfig = SystemDebuggerConfig()
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val jtagBridge = new JtagBridgeNoTap(
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c = jtagConfig,
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jtagClockDomain = jtagClockDomain
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)
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jtagBridge.io.ctrl << io.jtagInstruction
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val debugger = new SystemDebugger(jtagConfig)
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debugger.io.remote <> jtagBridge.io.remote
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cluster.io.debugBus << debugger.io.mem.toBmb()
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}
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val dBusDecoder = BmbDecoderOutOfOrder(
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p = cluster.io.dMem.p,
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mappings = Seq(DefaultMapping, p.liteDramMapping),
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@ -114,9 +128,39 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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val peripheralWishbone = peripheralArbiter.io.output.pipelined(cmdValid = true).toWishbone()
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io.peripheral << peripheralWishbone
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val plic = new Area{
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val priorityWidth = 2
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val gateways = for(i <- 1 until 32) yield PlicGatewayActiveHigh(
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source = io.interrupts(i),
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id = i,
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priorityWidth = priorityWidth
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)
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val bus = WishboneSlaveFactory(io.plic)
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val targets = for(i <- 0 until cpuCount) yield new Area{
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val machine = PlicTarget(
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gateways = gateways,
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priorityWidth = priorityWidth
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)
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val supervisor = PlicTarget(
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gateways = gateways,
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priorityWidth = priorityWidth
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)
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cluster.io.externalInterrupts(i) := machine.iep
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cluster.io.externalSupervisorInterrupts(i) := supervisor.iep
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}
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val bridge = PlicMapper(bus, PlicMapping.sifive)(
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gateways = gateways,
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targets = targets.flatMap(t => List(t.machine, t.supervisor))
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)
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}
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}
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//ifconfig eth0 192.168.0.50 netmask 255.255.255.0 up
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object VexRiscvLitexSmpClusterGen extends App {
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for(cpuCount <- List(1,2,4,8)) {
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def parameter = VexRiscvLitexSmpClusterParameter(
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@ -136,7 +180,8 @@ object VexRiscvLitexSmpClusterGen extends App {
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def dutGen = {
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val toplevel = VexRiscvLitexSmpCluster(
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p = parameter,
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
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jtagClockDomain = ClockDomain.external("jtag", withReset = false)
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)
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toplevel
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}
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@ -175,7 +220,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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def dutGen = {
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val top = VexRiscvLitexSmpCluster(
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p = parameter,
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
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jtagClockDomain = ClockDomain.external("jtag", withReset = false)
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)
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top.rework{
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top.io.clint.setAsDirectionLess.allowDirectionLessIo
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@ -216,8 +262,7 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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dut.io.iMem.simSlave(ram, dut.clockDomain)
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dut.io.dMem.simSlave(ram, dut.clockDomain, dut.dMemBridge.unburstified)
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dut.io.externalInterrupts #= 0
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dut.io.externalSupervisorInterrupts #= 0
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dut.io.interrupts #= 0
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dut.clockDomain.onFallingEdges{
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if(dut.io.peripheral.CYC.toBoolean){
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@ -3,13 +3,19 @@ package vexriscv.demo.smp
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import spinal.core._
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import spinal.lib.bus.bmb._
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig, WishboneSlaveFactory}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.{Jtag, JtagTap, JtagTapInstructionCtrl}
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import spinal.lib._
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import spinal.lib.blackbox.xilinx.s7.BSCANE2
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import spinal.lib.bus.bmb.sim.{BmbMemoryMultiPort, BmbMemoryTester}
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import spinal.lib.bus.misc.{AddressMapping, DefaultMapping, SizeMapping}
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import spinal.lib.com.jtag.sim.JtagTcp
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import spinal.lib.com.jtag.xilinx.Bscane2BmbMaster
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import spinal.lib.eda.bench.Bench
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import spinal.lib.misc.Clint
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import spinal.lib.misc.plic.{PlicGatewayActiveHigh, PlicMapper, PlicMapping, PlicTarget}
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import spinal.lib.sim.{SimData, SparseMemory, StreamDriver, StreamMonitor, StreamReadyRandomizer}
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import spinal.lib.system.debugger.{JtagBridgeNoTap, SystemDebugger, SystemDebuggerConfig}
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import sun.jvm.hotspot.oops.DataLayout
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import vexriscv.demo.smp.VexRiscvLitexSmpMpClusterOpenSbi.{cpuCount, parameter}
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import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
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import vexriscv.{VexRiscv, VexRiscvConfig}
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@ -24,8 +30,9 @@ case class VexRiscvLitexSmpMpClusterParameter( cluster : VexRiscvSmpClusterParam
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liteDramMapping : AddressMapping)
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//addAttribute("""mark_debug = "true"""")
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case class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter,
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debugClockDomain : ClockDomain) extends Component{
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class VexRiscvLitexSmpMpCluster(val p : VexRiscvLitexSmpMpClusterParameter,
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val debugClockDomain : ClockDomain,
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val jtagClockDomain : ClockDomain) extends Component{
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val peripheralWishboneConfig = WishboneConfig(
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addressWidth = 30,
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@ -43,23 +50,48 @@ case class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter,
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val iMem = Vec(master(LiteDramNative(p.liteDram)), cpuCount)
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val peripheral = master(Wishbone(peripheralWishboneConfig))
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val clint = slave(Wishbone(Clint.getWisboneConfig()))
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val externalInterrupts = in Bits(p.cluster.cpuConfigs.size bits)
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val externalSupervisorInterrupts = in Bits(p.cluster.cpuConfigs.size bits)
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val jtag = slave(Jtag())
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val plic = slave(Wishbone(WishboneConfig(addressWidth = 20, dataWidth = 32)))
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val interrupts = in Bits(32 bits)
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val jtagInstruction = slave(JtagTapInstructionCtrl())
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val debugReset = out Bool()
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}
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val clint = Clint(cpuCount)
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clint.driveFrom(WishboneSlaveFactory(io.clint))
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val cluster = VexRiscvSmpCluster(p.cluster, debugClockDomain)
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cluster.io.externalInterrupts <> io.externalInterrupts
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cluster.io.externalSupervisorInterrupts <> io.externalSupervisorInterrupts
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cluster.io.jtag <> io.jtag
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cluster.io.debugReset <> io.debugReset
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cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
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cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
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cluster.io.time := clint.time
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val debug = debugClockDomain on new Area{
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val jtagConfig = SystemDebuggerConfig()
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val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
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jtagBridge.io.ctrl << io.jtagInstruction
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val debugger = new SystemDebugger(jtagConfig)
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debugger.io.remote <> jtagBridge.io.remote
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cluster.io.debugBus << debugger.io.mem.toBmb()
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// io.jtagInstruction.allowDirectionLessIo.setAsDirectionLess
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// val bridge = Bscane2BmbMaster(1)
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// cluster.io.debugBus << bridge.io.bmb
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// val bscane2 = BSCANE2(usedId)
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// val jtagClockDomain = ClockDomain(bscane2.TCK)
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//
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// val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
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// jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl()
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//
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// val debugger = new SystemDebugger(jtagConfig)
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// debugger.io.remote <> jtagBridge.io.remote
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//
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// io.bmb << debugger.io.mem.toBmb()
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}
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val dBusDecoder = BmbDecoderOutOfOrder(
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p = cluster.io.dMem.p,
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mappings = Seq(DefaultMapping, p.liteDramMapping),
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@ -116,6 +148,38 @@ case class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter,
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val dMemBridge = for(id <- 0 until cpuCount) yield {
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io.dMem(id).fromBmb(dBusDemux.io.outputs(id), wdataFifoSize = 32, rdataFifoSize = 32)
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}
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val plic = new Area{
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val priorityWidth = 2
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val gateways = for(i <- 1 until 32) yield PlicGatewayActiveHigh(
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source = io.interrupts(i),
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id = i,
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priorityWidth = priorityWidth
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)
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val bus = WishboneSlaveFactory(io.plic)
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val targets = for(i <- 0 until cpuCount) yield new Area{
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val machine = PlicTarget(
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gateways = gateways,
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priorityWidth = priorityWidth
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)
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val supervisor = PlicTarget(
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gateways = gateways,
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priorityWidth = priorityWidth
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)
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cluster.io.externalInterrupts(i) := machine.iep
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cluster.io.externalSupervisorInterrupts(i) := supervisor.iep
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}
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val bridge = PlicMapper(bus, PlicMapping.sifive)(
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gateways = gateways,
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targets = targets.flatMap(t => List(t.machine, t.supervisor))
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)
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}
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//
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// io.dMem.foreach(_.cmd.valid.addAttribute("""mark_debug = "true""""))
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// io.dMem.foreach(_.cmd.ready.addAttribute("""mark_debug = "true""""))
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@ -145,9 +209,10 @@ object VexRiscvLitexSmpMpClusterGen extends App {
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)
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def dutGen = {
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val toplevel = VexRiscvLitexSmpMpCluster(
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val toplevel = new VexRiscvLitexSmpMpCluster(
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p = parameter,
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
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jtagClockDomain = ClockDomain.external("jtag", withReset = false)
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)
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toplevel
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}
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@ -185,10 +250,20 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
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|||
)
|
||||
|
||||
def dutGen = {
|
||||
val top = VexRiscvLitexSmpMpCluster(
|
||||
val top = new VexRiscvLitexSmpMpCluster(
|
||||
p = parameter,
|
||||
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
|
||||
)
|
||||
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
|
||||
jtagClockDomain = ClockDomain.external("jtag", withReset = false)
|
||||
){
|
||||
io.jtagInstruction.allowDirectionLessIo.setAsDirectionLess
|
||||
val jtag = slave(Jtag())
|
||||
jtagClockDomain.readClockWire.setAsDirectionLess() := jtag.tck
|
||||
val jtagLogic = jtagClockDomain on new Area{
|
||||
val tap = new JtagTap(jtag, 4)
|
||||
val idcodeArea = tap.idcode(B"x10001FFF")(1)
|
||||
val wrapper = tap.map(io.jtagInstruction, instructionId = 2)
|
||||
}
|
||||
}
|
||||
top.rework{
|
||||
top.io.clint.setAsDirectionLess.allowDirectionLessIo
|
||||
top.io.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()
|
||||
|
|
@ -217,6 +292,7 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
|
|||
dut.debugClockDomain.resetSim #= false
|
||||
}
|
||||
|
||||
JtagTcp(dut.jtag, 10*20)
|
||||
|
||||
val ram = SparseMemory()
|
||||
ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
|
||||
|
|
@ -229,8 +305,8 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
|
|||
dut.io.dMem(id).simSlave(ram, dut.clockDomain)
|
||||
}
|
||||
|
||||
dut.io.externalInterrupts #= 0
|
||||
dut.io.externalSupervisorInterrupts #= 0
|
||||
dut.io.interrupts #= 0
|
||||
|
||||
|
||||
// val stdin = mutable.Queue[Byte]()
|
||||
// def stdInPush(str : String) = stdin ++= str.toCharArray.map(_.toByte)
|
||||
|
|
@ -272,7 +348,7 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
|
|||
|
||||
fork{
|
||||
val at = 0
|
||||
val duration = 0
|
||||
val duration = 1000
|
||||
while(simTime() < at*1000000l) {
|
||||
disableSimWave()
|
||||
sleep(100000 * 10)
|
||||
|
|
|
|||
Loading…
Reference in New Issue