Rename SimpleBus into PipelinedMemoryBus
Move PipelinedMemoryBus into SpinalHDL lib
This commit is contained in:
Dolu1990
parent
2f6a2dfccc
commit
b1b7da4f10
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@ -29,16 +29,16 @@ lazy val root = (project in file(".")).
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version := "1.0.0"
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)),
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libraryDependencies ++= Seq(
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.2",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.2",
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// "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.2.2",
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// "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.2.2",
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"org.scalatest" % "scalatest_2.11" % "2.2.1",
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"org.yaml" % "snakeyaml" % "1.8"
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),
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name := "VexRiscv"
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)/*.dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib)
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).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib)
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lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "SpinalHDL-sim")
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lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "SpinalHDL-core")
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lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib")*/
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lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "SpinalHDL-lib")
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addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
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@ -4,8 +4,9 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba3.apb._
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.bus.simple.PipelinedMemoryBus
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.spi.ddr.SpiDdrMaster
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import spinal.lib.com.spi.ddr.SpiXdrMaster
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import spinal.lib.com.uart._
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import spinal.lib.io.{InOutWrapper, TriStateArray}
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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@ -13,6 +14,7 @@ import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import spinal.lib.com.spi.ddr._
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import spinal.lib.bus.simple._
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import scala.collection.mutable.ArrayBuffer
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/**
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@ -39,7 +41,7 @@ case class MuraxConfig(coreFrequency : HertzNumber,
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pipelineApbBridge : Boolean,
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gpioWidth : Int,
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uartCtrlConfig : UartCtrlMemoryMappedConfig,
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xipConfig : SpiDdrMasterCtrl.MemoryMappingParameters,
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xipConfig : SpiXdrMasterCtrl.MemoryMappingParameters,
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hardwareBreakpointCount : Int,
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cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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@ -59,11 +61,11 @@ object MuraxConfig{
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pipelineMainBus = false,
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pipelineApbBridge = true,
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gpioWidth = 32,
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xipConfig = ifGen(withXip) (SpiDdrMasterCtrl.MemoryMappingParameters(
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SpiDdrMasterCtrl.Parameters(8, 12, SpiDdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
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xipConfig = ifGen(withXip) (SpiXdrMasterCtrl.MemoryMappingParameters(
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SpiXdrMasterCtrl.Parameters(8, 12, SpiXdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiDdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
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xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, dataWidth = 32)
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)),
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hardwareBreakpointCount = if(withXip) 3 else 0,
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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@ -163,7 +165,7 @@ case class Murax(config : MuraxConfig) extends Component{
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val gpioA = master(TriStateArray(gpioWidth bits))
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val uart = master(Uart())
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val xip = ifGen(genXip)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
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val xip = ifGen(genXip)(master(SpiXdrMaster(xipConfig.ctrl.spi)))
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}
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@ -207,14 +209,14 @@ case class Murax(config : MuraxConfig) extends Component{
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)
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val system = new ClockingArea(systemClockDomain) {
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val simpleBusConfig = SimpleBusConfig(
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val pipelinedMemoryBusConfig = PipelinedMemoryBusConfig(
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addressWidth = 32,
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dataWidth = 32
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)
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//Arbiter of the cpu dBus/iBus to drive the mainBus
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//Priority to dBus, !! cmd transactions can change on the fly !!
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val mainBusArbiter = new MuraxMasterArbiter(simpleBusConfig)
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val mainBusArbiter = new MuraxMasterArbiter(pipelinedMemoryBusConfig)
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//Instanciate the CPU
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val cpu = new VexRiscv(
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@ -252,23 +254,23 @@ case class Murax(config : MuraxConfig) extends Component{
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//****** MainBus slaves ********
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val mainBusMapping = ArrayBuffer[(SimpleBus,SizeMapping)]()
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val ram = new MuraxSimpleBusRam(
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val mainBusMapping = ArrayBuffer[(PipelinedMemoryBus,SizeMapping)]()
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val ram = new MuraxPipelinedMemoryBusRam(
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onChipRamSize = onChipRamSize,
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onChipRamHexFile = onChipRamHexFile,
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simpleBusConfig = simpleBusConfig
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pipelinedMemoryBusConfig = pipelinedMemoryBusConfig
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)
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mainBusMapping += ram.io.bus -> (0x80000000l, onChipRamSize)
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val apbBridge = new MuraxSimpleBusToApbBridge(
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val apbBridge = new MuraxPipelinedMemoryBusToApbBridge(
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apb3Config = Apb3Config(
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addressWidth = 20,
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dataWidth = 32
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),
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pipelineBridge = pipelineApbBridge,
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simpleBusConfig = simpleBusConfig
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pipelinedMemoryBusConfig = pipelinedMemoryBusConfig
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)
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mainBusMapping += apbBridge.io.simpleBus -> (0xF0000000l, 1 MB)
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mainBusMapping += apbBridge.io.pipelinedMemoryBus -> (0xF0000000l, 1 MB)
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@ -288,15 +290,15 @@ case class Murax(config : MuraxConfig) extends Component{
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apbMapping += timer.io.apb -> (0x20000, 4 kB)
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val xip = ifGen(genXip)(new Area{
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val ctrl = Apb3SpiDdrMasterCtrl(xipConfig)
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val ctrl = Apb3SpiXdrMasterCtrl(xipConfig)
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ctrl.io.spi <> io.xip
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externalInterrupt setWhen(ctrl.io.interrupt)
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apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)
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val accessBus = new SimpleBus(SimpleBusConfig(24,32))
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val accessBus = new PipelinedMemoryBus(PipelinedMemoryBusConfig(24,32))
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mainBusMapping += accessBus -> (0xE0000000l, 16 MB)
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ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.wr)
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ctrl.io.xip.cmd.valid <> (accessBus.cmd.valid && !accessBus.cmd.write)
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ctrl.io.xip.cmd.ready <> accessBus.cmd.ready
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ctrl.io.xip.cmd.payload <> accessBus.cmd.address
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@ -316,7 +318,7 @@ case class Murax(config : MuraxConfig) extends Component{
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)
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val mainBusDecoder = new Area {
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val logic = new MuraxSimpleBusDecoder(
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val logic = new MuraxPipelinedMemoryBusDecoder(
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master = mainBusArbiter.io.masterBus,
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specification = mainBusMapping,
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pipelineMaster = pipelineMainBus
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@ -7,17 +7,18 @@ import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory}
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.misc.{HexTools, InterruptCtrl, Prescaler, Timer}
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import spinal.lib._
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import spinal.lib.bus.simple._
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import vexriscv.plugin.{DBusSimpleBus, IBusSimpleBus}
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class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
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class MuraxMasterArbiter(pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{
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val io = new Bundle{
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val iBus = slave(IBusSimpleBus(false))
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val dBus = slave(DBusSimpleBus())
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val masterBus = master(SimpleBus(simpleBusConfig))
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val masterBus = master(PipelinedMemoryBus(pipelinedMemoryBusConfig))
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}
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io.masterBus.cmd.valid := io.iBus.cmd.valid || io.dBus.cmd.valid
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io.masterBus.cmd.wr := io.dBus.cmd.valid && io.dBus.cmd.wr
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io.masterBus.cmd.write := io.dBus.cmd.valid && io.dBus.cmd.wr
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io.masterBus.cmd.address := io.dBus.cmd.valid ? io.dBus.cmd.address | io.iBus.cmd.pc
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io.masterBus.cmd.data := io.dBus.cmd.data
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io.masterBus.cmd.mask := io.dBus.cmd.size.mux(
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@ -31,7 +32,7 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
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val rspPending = RegInit(False) clearWhen(io.masterBus.rsp.valid)
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val rspTarget = RegInit(False)
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when(io.masterBus.cmd.fire && !io.masterBus.cmd.wr){
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when(io.masterBus.cmd.fire && !io.masterBus.cmd.write){
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rspTarget := io.dBus.cmd.valid
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rspPending := True
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}
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@ -52,18 +53,18 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
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}
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case class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
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case class MuraxPipelinedMemoryBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{
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val io = new Bundle{
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val bus = slave(SimpleBus(simpleBusConfig))
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val bus = slave(PipelinedMemoryBus(pipelinedMemoryBusConfig))
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}
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val ram = Mem(Bits(32 bits), onChipRamSize / 4)
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io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.wr) init(False)
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io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.write) init(False)
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io.bus.rsp.data := ram.readWriteSync(
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address = (io.bus.cmd.address >> 2).resized,
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data = io.bus.cmd.data,
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enable = io.bus.cmd.valid,
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write = io.bus.cmd.wr,
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write = io.bus.cmd.write,
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mask = io.bus.cmd.mask
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)
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io.bus.cmd.ready := True
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@ -95,42 +96,42 @@ case class Apb3Rom(onChipRamBinFile : String) extends Component{
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io.apb.PREADY := True
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}
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class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, simpleBusConfig : SimpleBusConfig) extends Component{
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assert(apb3Config.dataWidth == simpleBusConfig.dataWidth)
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class MuraxPipelinedMemoryBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{
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assert(apb3Config.dataWidth == pipelinedMemoryBusConfig.dataWidth)
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val io = new Bundle {
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val simpleBus = slave(SimpleBus(simpleBusConfig))
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val pipelinedMemoryBus = slave(PipelinedMemoryBus(pipelinedMemoryBusConfig))
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val apb = master(Apb3(apb3Config))
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}
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val simpleBusStage = SimpleBus(simpleBusConfig)
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simpleBusStage.cmd << (if(pipelineBridge) io.simpleBus.cmd.halfPipe() else io.simpleBus.cmd)
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simpleBusStage.rsp >-> io.simpleBus.rsp
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val pipelinedMemoryBusStage = PipelinedMemoryBus(pipelinedMemoryBusConfig)
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pipelinedMemoryBusStage.cmd << (if(pipelineBridge) io.pipelinedMemoryBus.cmd.halfPipe() else io.pipelinedMemoryBus.cmd)
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pipelinedMemoryBusStage.rsp >-> io.pipelinedMemoryBus.rsp
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val state = RegInit(False)
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simpleBusStage.cmd.ready := False
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pipelinedMemoryBusStage.cmd.ready := False
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io.apb.PSEL(0) := simpleBusStage.cmd.valid
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io.apb.PSEL(0) := pipelinedMemoryBusStage.cmd.valid
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io.apb.PENABLE := state
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io.apb.PWRITE := simpleBusStage.cmd.wr
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io.apb.PADDR := simpleBusStage.cmd.address.resized
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io.apb.PWDATA := simpleBusStage.cmd.data
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io.apb.PWRITE := pipelinedMemoryBusStage.cmd.write
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io.apb.PADDR := pipelinedMemoryBusStage.cmd.address.resized
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io.apb.PWDATA := pipelinedMemoryBusStage.cmd.data
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simpleBusStage.rsp.valid := False
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simpleBusStage.rsp.data := io.apb.PRDATA
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pipelinedMemoryBusStage.rsp.valid := False
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pipelinedMemoryBusStage.rsp.data := io.apb.PRDATA
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when(!state) {
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state := simpleBusStage.cmd.valid
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state := pipelinedMemoryBusStage.cmd.valid
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} otherwise {
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when(io.apb.PREADY){
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state := False
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simpleBusStage.rsp.valid := !simpleBusStage.cmd.wr
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simpleBusStage.cmd.ready := True
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pipelinedMemoryBusStage.rsp.valid := !pipelinedMemoryBusStage.cmd.write
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pipelinedMemoryBusStage.cmd.ready := True
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}
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}
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}
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class MuraxSimpleBusDecoder(master : SimpleBus, val specification : Seq[(SimpleBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
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val masterPipelined = SimpleBus(master.config)
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class MuraxPipelinedMemoryBusDecoder(master : PipelinedMemoryBus, val specification : Seq[(PipelinedMemoryBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
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val masterPipelined = PipelinedMemoryBus(master.config)
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if(!pipelineMaster) {
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masterPipelined.cmd << master.cmd
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masterPipelined.rsp >> master.rsp
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@ -151,7 +152,7 @@ class MuraxSimpleBusDecoder(master : SimpleBus, val specification : Seq[(SimpleB
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val noHit = !hits.orR
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masterPipelined.cmd.ready := (hits,slaveBuses).zipped.map(_ && _.cmd.ready).orR || noHit
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val rspPending = RegInit(False) clearWhen(masterPipelined.rsp.valid) setWhen(masterPipelined.cmd.fire && !masterPipelined.cmd.wr)
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val rspPending = RegInit(False) clearWhen(masterPipelined.rsp.valid) setWhen(masterPipelined.cmd.fire && !masterPipelined.cmd.write)
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val rspNoHit = RegNext(False) init(False) setWhen(noHit)
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val rspSourceId = RegNextWhen(OHToUInt(hits), masterPipelined.cmd.fire)
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masterPipelined.rsp.valid := slaveBuses.map(_.rsp.valid).orR || (rspPending && rspNoHit)
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@ -1,324 +0,0 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib.bus.misc._
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import spinal.lib._
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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case class SimpleBusConfig(addressWidth : Int, dataWidth : Int)
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case class SimpleBusCmd(config : SimpleBusConfig) extends Bundle{
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val wr = Bool
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val address = UInt(config.addressWidth bits)
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val data = Bits(config.dataWidth bits)
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val mask = Bits(4 bit)
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}
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case class SimpleBusRsp(config : SimpleBusConfig) extends Bundle{
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val data = Bits(config.dataWidth bits)
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}
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object SimpleBus{
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def apply(addressWidth : Int, dataWidth : Int) = new SimpleBus(SimpleBusConfig(addressWidth, dataWidth))
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}
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case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave {
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val cmd = Stream(SimpleBusCmd(config))
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val rsp = Flow(SimpleBusRsp(config))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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def <<(m : SimpleBus) : Unit = {
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val s = this
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assert(m.config.addressWidth >= s.config.addressWidth)
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assert(m.config.dataWidth == s.config.dataWidth)
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s.cmd.valid := m.cmd.valid
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s.cmd.wr := m.cmd.wr
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s.cmd.address := m.cmd.address.resized
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s.cmd.data := m.cmd.data
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s.cmd.mask := m.cmd.mask
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m.cmd.ready := s.cmd.ready
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m.rsp.valid := s.rsp.valid
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m.rsp.data := s.rsp.data
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}
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def >>(s : SimpleBus) : Unit = s << this
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def cmdM2sPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd.m2sPipe() >> ret.cmd
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this.rsp << ret.rsp
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ret
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}
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def cmdS2mPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd.s2mPipe() >> ret.cmd
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this.rsp << ret.rsp
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ret
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}
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def rspPipe(): SimpleBus = {
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val ret = cloneOf(this)
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this.cmd >> ret.cmd
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this.rsp << ret.rsp.stage()
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ret
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}
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}
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object SimpleBusArbiter{
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def apply(inputs : Seq[SimpleBus], pendingRspMax : Int, rspRouteQueue : Boolean, transactionLock : Boolean): SimpleBus = {
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val c = SimpleBusArbiter(inputs.head.config, inputs.size, pendingRspMax, rspRouteQueue, transactionLock)
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(inputs, c.io.inputs).zipped.foreach(_ <> _)
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c.io.output
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}
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}
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case class SimpleBusArbiter(simpleBusConfig : SimpleBusConfig, portCount : Int, pendingRspMax : Int, rspRouteQueue : Boolean, transactionLock : Boolean = true) extends Component{
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val io = new Bundle{
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val inputs = Vec(slave(SimpleBus(simpleBusConfig)), portCount)
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val output = master(SimpleBus(simpleBusConfig))
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}
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val logic = if(portCount == 1) new Area{
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io.output << io.inputs(0)
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} else new Area {
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val arbiterFactory = StreamArbiterFactory.lowerFirst
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if(transactionLock) arbiterFactory.transactionLock else arbiterFactory.noLock
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val arbiter = arbiterFactory.build(SimpleBusCmd(simpleBusConfig), portCount)
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(arbiter.io.inputs, io.inputs).zipped.foreach(_ <> _.cmd)
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val rspRouteOh = Bits(portCount bits)
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val rsp = if(!rspRouteQueue) new Area{
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assert(pendingRspMax == 1)
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val pending = RegInit(False) clearWhen(io.output.rsp.valid)
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val target = Reg(Bits(portCount bits))
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rspRouteOh := target
|
||||
when(io.output.cmd.fire && !io.output.cmd.wr){
|
||||
target := arbiter.io.chosenOH
|
||||
pending := True
|
||||
}
|
||||
io.output.cmd << arbiter.io.output.haltWhen(pending && !io.output.rsp.valid)
|
||||
} else new Area{
|
||||
val (outputCmdFork, routeCmdFork) = StreamFork2(arbiter.io.output)
|
||||
io.output.cmd << outputCmdFork
|
||||
|
||||
val rspRoute = routeCmdFork.translateWith(arbiter.io.chosenOH).throwWhen(routeCmdFork.wr).queueLowLatency(size = pendingRspMax, latency = 1)
|
||||
rspRoute.ready := io.output.rsp.valid
|
||||
rspRouteOh := rspRoute.payload
|
||||
}
|
||||
|
||||
for ((input, id) <- io.inputs.zipWithIndex) {
|
||||
input.rsp.valid := io.output.rsp.valid && rspRouteOh(id)
|
||||
input.rsp.payload := io.output.rsp.payload
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class SimpleBusSlaveFactory(bus: SimpleBus) extends BusSlaveFactoryDelayed{
|
||||
bus.cmd.ready := True
|
||||
|
||||
val readAtCmd = Flow(Bits(bus.config.dataWidth bits))
|
||||
val readAtRsp = readAtCmd.stage()
|
||||
|
||||
val askWrite = (bus.cmd.valid && bus.cmd.wr).allowPruning()
|
||||
val askRead = (bus.cmd.valid && !bus.cmd.wr).allowPruning()
|
||||
val doWrite = (askWrite && bus.cmd.ready).allowPruning()
|
||||
val doRead = (askRead && bus.cmd.ready).allowPruning()
|
||||
|
||||
bus.rsp.valid := readAtRsp.valid
|
||||
bus.rsp.data := readAtRsp.payload
|
||||
|
||||
readAtCmd.valid := doRead
|
||||
readAtCmd.payload := 0
|
||||
|
||||
def readAddress() : UInt = bus.cmd.address
|
||||
def writeAddress() : UInt = bus.cmd.address
|
||||
|
||||
override def readHalt(): Unit = bus.cmd.ready := False
|
||||
override def writeHalt(): Unit = bus.cmd.ready := False
|
||||
|
||||
override def build(): Unit = {
|
||||
super.doNonStopWrite(bus.cmd.data)
|
||||
|
||||
def doMappedElements(jobs : Seq[BusSlaveFactoryElement]) = super.doMappedElements(
|
||||
jobs = jobs,
|
||||
askWrite = askWrite,
|
||||
askRead = askRead,
|
||||
doWrite = doWrite,
|
||||
doRead = doRead,
|
||||
writeData = bus.cmd.data,
|
||||
readData = readAtCmd.payload
|
||||
)
|
||||
|
||||
switch(bus.cmd.address) {
|
||||
for ((address, jobs) <- elementsPerAddress if address.isInstanceOf[SingleMapping]) {
|
||||
is(address.asInstanceOf[SingleMapping].address) {
|
||||
doMappedElements(jobs)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for ((address, jobs) <- elementsPerAddress if !address.isInstanceOf[SingleMapping]) {
|
||||
when(address.hit(bus.cmd.address)){
|
||||
doMappedElements(jobs)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
override def busDataWidth: Int = bus.config.dataWidth
|
||||
override def wordAddressInc: Int = busDataWidth / 8
|
||||
}
|
||||
|
||||
case class SimpleBusDecoder(busConfig : SimpleBusConfig, mappings : Seq[AddressMapping], pendingMax : Int = 3) extends Component{
|
||||
val io = new Bundle {
|
||||
val input = slave(SimpleBus(busConfig))
|
||||
val outputs = Vec(master(SimpleBus(busConfig)), mappings.size)
|
||||
}
|
||||
val hasDefault = mappings.contains(DefaultMapping)
|
||||
val logic = if(hasDefault && mappings.size == 1){
|
||||
io.outputs(0) <> io.input
|
||||
} else new Area {
|
||||
val hits = Vec(Bool, mappings.size)
|
||||
for ((slaveBus, memorySpace, hit) <- (io.outputs, mappings, hits).zipped) yield {
|
||||
hit := (memorySpace match {
|
||||
case DefaultMapping => !hits.filterNot(_ == hit).orR
|
||||
case _ => memorySpace.hit(io.input.cmd.address)
|
||||
})
|
||||
slaveBus.cmd.valid := io.input.cmd.valid && hit
|
||||
slaveBus.cmd.payload := io.input.cmd.payload.resized
|
||||
}
|
||||
val noHit = if (!hasDefault) !hits.orR else False
|
||||
io.input.cmd.ready := (hits, io.outputs).zipped.map(_ && _.cmd.ready).orR || noHit
|
||||
|
||||
val rspPendingCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
|
||||
rspPendingCounter := rspPendingCounter + U(io.input.cmd.fire && !io.input.cmd.wr) - U(io.input.rsp.valid)
|
||||
val rspHits = RegNextWhen(hits, io.input.cmd.fire)
|
||||
val rspPending = rspPendingCounter =/= 0
|
||||
val rspNoHit = if (!hasDefault) !rspHits.orR else False
|
||||
io.input.rsp.valid := io.outputs.map(_.rsp.valid).orR || (rspPending && rspNoHit)
|
||||
io.input.rsp.payload := io.outputs.map(_.rsp.payload).read(OHToUInt(rspHits))
|
||||
|
||||
val cmdWait = (io.input.cmd.valid && rspPending && hits =/= rspHits) || rspPendingCounter === pendingMax
|
||||
when(cmdWait) {
|
||||
io.input.cmd.ready := False
|
||||
io.outputs.foreach(_.cmd.valid := False)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
object SimpleBusConnectors{
|
||||
def direct(m : SimpleBus, s : SimpleBus) : Unit = m >> s
|
||||
}
|
||||
|
||||
case class SimpleBusInterconnect(){
|
||||
case class MasterModel(var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct)
|
||||
case class SlaveModel(mapping : AddressMapping, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct, var transactionLock : Boolean = true)
|
||||
case class ConnectionModel(m : SimpleBus, s : SimpleBus, var connector : (SimpleBus,SimpleBus) => Unit = SimpleBusConnectors.direct)
|
||||
|
||||
val masters = mutable.LinkedHashMap[SimpleBus, MasterModel]()
|
||||
val slaves = mutable.LinkedHashMap[SimpleBus, SlaveModel]()
|
||||
val connections = ArrayBuffer[ConnectionModel]()
|
||||
var arbitrationPendingRspMaxDefault = 1
|
||||
var arbitrationRspRouteQueueDefault = false
|
||||
|
||||
def perfConfig(): Unit ={
|
||||
arbitrationPendingRspMaxDefault = 7
|
||||
arbitrationRspRouteQueueDefault = true
|
||||
}
|
||||
|
||||
def areaConfig(): Unit ={
|
||||
arbitrationPendingRspMaxDefault = 1
|
||||
arbitrationRspRouteQueueDefault = false
|
||||
}
|
||||
|
||||
def setConnector(bus : SimpleBus)( connector : (SimpleBus,SimpleBus) => Unit): Unit = (masters.get(bus), slaves.get(bus)) match {
|
||||
case (Some(m), _) => m.connector = connector
|
||||
case (None, Some(s)) => s.connector = connector
|
||||
}
|
||||
|
||||
def setConnector(m : SimpleBus, s : SimpleBus)(connector : (SimpleBus,SimpleBus) => Unit): Unit = connections.find(e => e.m == m && e.s == s) match {
|
||||
case Some(c) => c.connector = connector
|
||||
}
|
||||
|
||||
def addSlave(bus: SimpleBus,mapping: AddressMapping) : this.type = {
|
||||
slaves(bus) = SlaveModel(mapping)
|
||||
this
|
||||
}
|
||||
|
||||
def addSlaves(orders : (SimpleBus,AddressMapping)*) : this.type = {
|
||||
orders.foreach(order => addSlave(order._1,order._2))
|
||||
this
|
||||
}
|
||||
|
||||
def noTransactionLockOn(slave : SimpleBus) : Unit = slaves(slave).transactionLock = false
|
||||
def noTransactionLockOn(slaves : Seq[SimpleBus]) : Unit = slaves.foreach(noTransactionLockOn(_))
|
||||
|
||||
|
||||
def addMaster(bus : SimpleBus, accesses : Seq[SimpleBus]) : this.type = {
|
||||
masters(bus) = MasterModel()
|
||||
for(s <- accesses) connections += ConnectionModel(bus, s)
|
||||
this
|
||||
}
|
||||
|
||||
def addMasters(specs : (SimpleBus,Seq[SimpleBus])*) : this.type = {
|
||||
specs.foreach(spec => addMaster(spec._1,spec._2))
|
||||
this
|
||||
}
|
||||
|
||||
def build(): Unit ={
|
||||
def applyName(bus : Bundle,name : String, onThat : Nameable) : Unit = {
|
||||
if(bus.component == Component.current)
|
||||
onThat.setCompositeName(bus,name)
|
||||
else if(bus.isNamed)
|
||||
onThat.setCompositeName(bus.component,bus.getName() + "_" + name)
|
||||
}
|
||||
|
||||
val connectionsInput = mutable.HashMap[ConnectionModel,SimpleBus]()
|
||||
val connectionsOutput = mutable.HashMap[ConnectionModel,SimpleBus]()
|
||||
for((bus, model) <- masters){
|
||||
val busConnections = connections.filter(_.m == bus)
|
||||
val busSlaves = busConnections.map(c => slaves(c.s))
|
||||
val decoder = new SimpleBusDecoder(bus.config, busSlaves.map(_.mapping))
|
||||
applyName(bus,"decoder",decoder)
|
||||
model.connector(bus, decoder.io.input)
|
||||
for((connection, decoderOutput) <- (busConnections, decoder.io.outputs).zipped) {
|
||||
connectionsInput(connection) = decoderOutput
|
||||
}
|
||||
}
|
||||
|
||||
for((bus, model) <- slaves){
|
||||
val busConnections = connections.filter(_.s == bus)
|
||||
val busMasters = busConnections.map(c => masters(c.m))
|
||||
val arbiter = new SimpleBusArbiter(bus.config, busMasters.size, arbitrationPendingRspMaxDefault, arbitrationRspRouteQueueDefault, model.transactionLock)
|
||||
applyName(bus,"arbiter",arbiter)
|
||||
model.connector(arbiter.io.output, bus)
|
||||
for((connection, arbiterInput) <- (busConnections, arbiter.io.inputs).zipped) {
|
||||
connectionsOutput(connection) = arbiterInput
|
||||
}
|
||||
}
|
||||
|
||||
for(connection <- connections){
|
||||
val m = connectionsInput(connection)
|
||||
val s = connectionsOutput(connection)
|
||||
if(m.config == s.config) {
|
||||
connection.connector(m, s)
|
||||
}else{
|
||||
val tmp = cloneOf(s)
|
||||
m >> tmp //Adapte the bus kind.
|
||||
connection.connector(tmp,s)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//Will make SpinalHDL calling the build function at the end of the current component elaboration
|
||||
Component.current.addPrePopTask(build)
|
||||
}
|
||||
|
|
@ -6,7 +6,7 @@ import spinal.lib._
|
|||
import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared}
|
||||
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
|
||||
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
|
||||
import vexriscv.demo.SimpleBus
|
||||
import spinal.lib.bus.simple._
|
||||
|
||||
case class DataCacheConfig( cacheSize : Int,
|
||||
bytePerLine : Int,
|
||||
|
|
@ -346,8 +346,8 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
|
|||
|
||||
|
||||
|
||||
def toSimpleBus(): SimpleBus = {
|
||||
val bus = SimpleBus(32,32)
|
||||
def toPipelinedMemoryBus(): PipelinedMemoryBus = {
|
||||
val bus = PipelinedMemoryBus(32,32)
|
||||
|
||||
val counter = Reg(UInt(log2Up(p.burstSize) bits)) init(0)
|
||||
when(bus.cmd.fire){ counter := counter + 1 }
|
||||
|
|
@ -355,7 +355,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
|
|||
|
||||
bus.cmd.valid := cmd.valid
|
||||
bus.cmd.address := (cmd.address(31 downto 2) | counter.resized) @@ U"00"
|
||||
bus.cmd.wr := cmd.wr
|
||||
bus.cmd.write := cmd.wr
|
||||
bus.cmd.mask := cmd.mask
|
||||
bus.cmd.data := cmd.data
|
||||
cmd.ready := bus.cmd.ready && (cmd.wr || counter === cmd.length)
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ import spinal.lib._
|
|||
import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4ReadOnly}
|
||||
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
|
||||
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
|
||||
import vexriscv.demo.{SimpleBus, SimpleBusConfig}
|
||||
import spinal.lib.bus.simple._
|
||||
|
||||
|
||||
case class InstructionCacheConfig( cacheSize : Int,
|
||||
|
|
@ -46,7 +46,7 @@ case class InstructionCacheConfig( cacheSize : Int,
|
|||
constantBurstBehavior = true
|
||||
)
|
||||
|
||||
def getSimpleBusConfig() = SimpleBusConfig(
|
||||
def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
|
||||
addressWidth = 32,
|
||||
dataWidth = 32
|
||||
)
|
||||
|
|
@ -185,13 +185,13 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
|
|||
}
|
||||
|
||||
|
||||
def toSimpleBus(): SimpleBus = {
|
||||
val simpleBusConfig = p.getSimpleBusConfig()
|
||||
val bus = SimpleBus(simpleBusConfig)
|
||||
def toPipelinedMemoryBus(): PipelinedMemoryBus = {
|
||||
val pipelinedMemoryBusConfig = p.getPipelinedMemoryBusConfig()
|
||||
val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
|
||||
val counter = Counter(p.burstSize, bus.cmd.fire)
|
||||
bus.cmd.valid := cmd.valid
|
||||
bus.cmd.address := cmd.address(31 downto widthOf(counter.value) + 2) @@ counter @@ U"00"
|
||||
bus.cmd.wr := False
|
||||
bus.cmd.write := False
|
||||
bus.cmd.mask.assignDontCare()
|
||||
bus.cmd.data.assignDontCare()
|
||||
cmd.ready := counter.willOverflow
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ import spinal.lib._
|
|||
import spinal.lib.bus.amba4.axi._
|
||||
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
|
||||
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
|
||||
import vexriscv.demo.SimpleBus
|
||||
import spinal.lib.bus.simple._
|
||||
import vexriscv.ip.DataCacheMemCmd
|
||||
|
||||
|
||||
|
|
@ -176,11 +176,11 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
|
|||
rsp.error := False //TODO
|
||||
bus
|
||||
}
|
||||
|
||||
def toSimpleBus() : SimpleBus = {
|
||||
val bus = SimpleBus(32,32)
|
||||
|
||||
def toPipelinedMemoryBus() : PipelinedMemoryBus = {
|
||||
val bus = PipelinedMemoryBus(32,32)
|
||||
bus.cmd.valid := cmd.valid
|
||||
bus.cmd.wr := cmd.wr
|
||||
bus.cmd.write := cmd.wr
|
||||
bus.cmd.address := cmd.address.resized
|
||||
bus.cmd.data := cmd.data
|
||||
bus.cmd.mask := cmd.size.mux(
|
||||
|
|
|
|||
|
|
@ -6,8 +6,7 @@ import spinal.lib._
|
|||
import spinal.lib.bus.amba4.axi._
|
||||
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
|
||||
import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
|
||||
import vexriscv.demo.SimpleBus
|
||||
|
||||
import spinal.lib.bus.simple._
|
||||
|
||||
|
||||
case class IBusSimpleCmd() extends Bundle{
|
||||
|
|
@ -136,11 +135,11 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
|
|||
bus
|
||||
}
|
||||
|
||||
def toSimpleBus(): SimpleBus = {
|
||||
val bus = SimpleBus(32,32)
|
||||
def toPipelinedMemoryBus(): PipelinedMemoryBus = {
|
||||
val bus = PipelinedMemoryBus(32,32)
|
||||
bus.cmd.arbitrationFrom(cmd)
|
||||
bus.cmd.address := cmd.pc.resized
|
||||
bus.cmd.wr := False
|
||||
bus.cmd.write := False
|
||||
bus.cmd.mask.assignDontCare()
|
||||
bus.cmd.data.assignDontCare()
|
||||
rsp.valid := bus.rsp.valid
|
||||
|
|
|
|||
Loading…
Reference in New Issue