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Pradeep2004
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1. INTRODUCTION
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The traditional way of debugging an SoC which is programmed inside a FPGA was by using a JTAG Adapter which comes with an FTDI Chip. In recent times, modern FPGA’s come with an integrated FTDI chip which makes debugging easy with only a USB cable.
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In recent times, modern FPGA’s come with an integrated FTDI chip which makes debugging easy with only a USB cable, thereby reducing an unnecessary extra hardware (JTAG Adapter).
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In this document, I am going to guide you through the steps in an experiment which I conducted along with my supervisor to debug an SoC named MURAX without using an external JTAG adapter on ARTY A7 FPGA.
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@ -8,73 +8,131 @@ In this document, I am going to guide you through the steps in an experiment whi
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The BSCANE2 allows access between the internal FPGA logic and the JTAG Boundary Scan logic controller. This allows for communication between the internal running design and the dedicated JTAG pins of the FPGA.
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2.1 Steps to create Bscane2
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Steps to create Bscane2
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• After cloning all the files from https://github.com/SpinalHDL/VexRiscv, go to this path : src/main/scala/vexriscv/demo and find the Murax.scala file.
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• After cloning all the files from https://github.com/SpinalHDL/VexRiscv, go to this path : src/main/scala/vexriscv/demo and find the Murax.scala file.
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• Comment out the following lines to remove the toplevel jtag I/O pins in Murax.scala file
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val jtag = slave(Jtag())
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val jtagClkBuffer = SB_GB()
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jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.jtag_tck
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jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck
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murax.io.jtag.tdi <> io.jtag_tdi
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murax.io.jtag.tdo <> io.jtag_tdo
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murax.io.jtag.tms <> io.jtag_tms
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• Comment out the following lines to remove the toplevel jtag I/O pins in Murax.scala
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val jtag = slave(Jtag())
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val jtagClkBuffer = SB_GB()
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jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.jtag_tck
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jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck
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murax.io.jtag.tdi <> io.jtag_tdi
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murax.io.jtag.tdo <> io.jtag_tdo
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murax.io.jtag.tms <> io.jtag_tms
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• In the Murax.scala file, delete line number 253 and add the following lines :
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val jtagCtrl = JtagTapInstructionCtrl()
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val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
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jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
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• In the Murax.scala file, delete the below line:
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io.jtag <> plugin.io.bus.fromJtag()
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And add the following lines :
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val jtagCtrl = JtagTapInstructionCtrl()
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val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
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jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
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• Add the following import statement at the beginning in Murax.scala :
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import spinal.lib.com.jtag.JtagTapInstructionCtrl
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By deleting the line (io.jtag <> plugin.io.bus.fromJtag() ) and adding the above lines, the Murax SoC’s Jtag ports are removed and a Bscane2 bridge will be created inside the Murax SoC itself, thereby avoiding to add the Bscane2 IP while programming the FPGA.
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• Then to generate the SoC with a demo program already in ram, run:
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sbt "runMain vexriscv.demo.MuraxWithRamInit"
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• Add the following import statement at the beginning in Murax.scala :
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import spinal.lib.com.jtag.JtagTapInstructionCtrl
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• Then to generate the SoC with a demo program already in ram, run:
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sbt "runMain vexriscv.demo.MuraxWithRamInit"
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• A verilog file will be generated with the name Murax.v and four .bin files will be generated inside VexRiscv folder which can be used to program the FPGA. Inside the Murax.v file, we can see that the Bscane2 ports will be instantiated, confirming that the Bscane2 has been created within the Murax SoC to debug it.
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• A verilog file will be generated with the name Murax.v and four .bin files will be generated inside VexRiscv folder which can be used to program the FPGA. Inside the Murax.v file, we can see that the Bscane2 ports will be instantiated, confirming that the Bscane2 has been created within the Murax SoC to debug it.
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3. Programming Arty A7 FPGA
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There are many applications to program a FPGA. I am using Xilinx Vivado 2020 Application to program the FPGA.
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There are many applications to program a FPGA. I am using Xilinx Vivado 2020 Application to program the FPGA, which is an open source application and is readily available in Xilinx website and free of cost to download.
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3.1 Steps involved to program the FPGA
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Steps involved to program the FPGA
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• Create a new project and choose the board which are using and choose the constraint file.
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• Create a new project and choose the board which are using and choose the constraint file.
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• As, I mentioned in the previous section a verilog file and four .bin files will be generated in the Vexriscv folder. Copy these files and paste them inside your vivado project in this path : project_name.srcs\sources_1\imports\Downloads
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• As, I mentioned in the previous section a verilog file and four .bin files will be generated in the Vexriscv folder. Copy these files and paste them inside your vivado project in this path : project_name.srcs\sources_1\imports\Downloads
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• Create a toplevel file by instantiating Murax I/O ports in it to blink the LED’s on the FPGA. (Note : The program to blink the LED’s is already present in Murax.v file). The toplevel file and constraint file, if required can be found here : https://github.com/SpinalHDL/VexRiscv/tree/master/scripts/Murax/arty_a7 , but make sure all the jtag ports of Murax are commented or deleted in the toplevel file.
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• Create a toplevel file by instantiating Murax I/O ports in it to blink the LED’s on the FPGA. (Note : The program to blink the LED’s is already present in Murax.v file). The toplevel file and constraint file, if required can be found in this path :VexRiscv/scripts/Murax/arty_a7 , but make sure all the jtag ports of Murax are commented or deleted in the toplevel file.
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• Next, click Generate Bitstream and program the FPGA with the bit file. You can see the LED’s blink and Murax SoC has been programmed into the FPGA.
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• The lines to remove from toplevel file are :
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reg tesic_tck,tesic_tms,tesic_tdi;
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wire tesic_tdo;
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reg soc_tck,soc_tms,soc_tdi;
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wire soc_tdo;
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always @(*) begin
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{soc_tck, soc_tms, soc_tdi } = {tck,tms,tdi};
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tdo = soc_tdo;
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end
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.io_jtag_tck(soc_tck),
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.io_jtag_tdi(soc_tdi),
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.io_jtag_tdo(soc_tdo),
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.io_jtag_tms(soc_tms),
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• Next, click Generate Bitstream and program the FPGA with the bit file. You can see the LED’s blink and Murax SoC has been programmed into the FPGA.
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4. Debugging via OpenOCD GDB in Linux
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• In a new terminal in Linux, after cloning and setting up openocd with the steps provided in this link : https://github.com/SpinalHDL/openocd_riscv , run the below command to establish a openocd connection with Jtag of FPGA.
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• To run openocd :
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Use the below command :
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src/openocd -c "set CPU0_YAML ..VexRiscv/cpu0.yaml" -f tcl/interface/usb_connect.cfg -f tcl/interface/soc_init.cfg
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• In a new terminal in Linux, after cloning and setting up openocd with the steps provided in this link : https://github.com/SpinalHDL/openocd_riscv , run the below command to establish a openocd connection with JTAG of FPGA.
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• You basically have to provide 2 files.
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• You basically have to provide 2 files.
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usb_connect.cfg => interface configuration
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soc_init.cfg => take over the control of the CPU.
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soc_init.cfg => take over the control of the CPU
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• For usb_connect.cfg
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you can take it from https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/digilent/ArtyA7SmpLinux/openocd/usb_connect.cfg (without modifications i would say)
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• For usb_connect.cfg
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you can take it from https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/digilent/ArtyA7SmpLinux/openocd/usb_connect.cfg (without modifications I would say, but make sure to check the entire path in your system for the files
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xilinx-xc7.cfg and jtagspi.cfg) and write it as below, remove the word “find” and the square brackets.
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source ../openocd_riscv/tcl/cpld/xilinx-xc7.cfg
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source .. /openocd_riscv/tcl/cpld/jtagspi.cfg
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• For soc_init.cfg
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• For soc_init.cfg
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https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/digilent/ArtyA7SmpLinux/openocd/soc_init.cfg
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You can take it but you need to : set cpu_count to 1 and remove Line 22 to 35.
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You can take it but you need to : set cpu_count to 1 and remove Line 22 to 35 as shown below :
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set cpu_count 1
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• Then, after openocd is running, in new terminal, follow the below commands in VexriscvSocSoftware folder ( https://github.com/SpinalHDL/VexRiscvSocSoftware )
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for {set i 0} {$i < $cpu_count} {incr i} {
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target create saxon.cpu$i vexriscv -endian little -chain-position $TAP_NAME -coreid $i -dbgbase [expr $i*0x1000+0x10B80000]
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vexriscv readWaitCycles 40
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vexriscv cpuConfigFile $CPU0_YAML
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if {$SPINAL_SIM != "yes"} {
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vexriscv jtagMapping 3 3 0 1 2 2
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}
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}
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• Go to the path VexRiscvSocSoftware/projects/murax/demo/build and then give the below commands :
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for {set i 0} {$i < $cpu_count} {incr i} {
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targets saxon.cpu$i
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poll_period 50
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init
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soft_reset_halt
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}
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puts done
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• To run openocd :
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Use the below command :
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src/openocd -c "set CPU0_YAML ../VexRiscv/cpu0.yaml" -f tcl/interface/usb_connect.cfg -f tcl/interface/soc_init.cfg
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• Prequisites to have before executing the next steps can be found here :
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https://github.com/riscv/riscv-gnu-toolchain
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• Then, after openocd is running, in new terminal, follow the below commands in VexriscvSocSoftware folder ( https://github.com/SpinalHDL/VexRiscvSocSoftware ).
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• Go to the path VexRiscvSocSoftware/projects/murax/demo/build and then give the below commands :
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riscv64-unknown-elf-gdb demo.elf
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- This command will initiate the already written demo program to blink the LED’s on the FPGA.
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target remote localhost:3333
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- This command will connect the GDB server
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load
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- This command will load the program into the FPGA
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riscv64-unknown-elf-gdb demo.elf
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target remote localhost:3333
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monitor reset halt
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load
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continue
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- This command will halt the blinking of LED’s
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• After giving the monitor reset halt command you can see that the LED’s stop blinking and when the continue command is given the LED’s start continuing from the point where they stopped.
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continue
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- This command will continue the blinking of LED’s from the point it stopped.
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By,
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Pradeep Krishnamurthy - Research Assistant, Offis e.V
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Frank Poppen - Senior Research Engineer, Offis e.V
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