SimpleMul core.
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package vexriscv.demo
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import vexriscv.plugin._
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
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import spinal.core._
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/**
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* Created by spinalvm on 15.06.17.
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*/
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object GenFullNoMmuNoCacheSimpleMul extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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plugins = List(
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = false,
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prediction = STATIC,
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catchAccessFault = false,
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compressedGen = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrelShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulSimplePlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.small),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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SpinalVerilog(cpu())
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}
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