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VexRiscv
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#60 user space reached 

/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
This commit is contained in:
Dolu1990 2019-03-27 00:26:51 +01:00
parent 94fc2c3ecf
commit b69c474fa2
8 changed files with 485 additions and 688 deletions
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1
.gitignore vendored
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@ -40,6 +40,7 @@ obj_dir
*.yaml
*.memTrace
*.regTrace
*.debugTrace
*.tcl
*.o
*.bin

910
src/main/c/emulator/build/emulator.asm
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File diff suppressed because it is too large Load Diff

179
src/main/c/emulator/build/emulator.hex
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@ -1,10 +1,10 @@
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2
src/main/c/emulator/makefile
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@ -1,5 +1,5 @@
PROJ_NAME=emulator
DEBUG=yes
DEBUG=no
MULDIV=no
COMPRESSED=no
STANDALONE = ..

6
src/main/c/emulator/src/main.c
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@ -14,7 +14,7 @@ void init() {
csr_write(mstatus, 0x0800 | MSTATUS_MPIE);
csr_write(mie, 0);
csr_write(mepc, OS_CALL);
csr_write(medeleg, MEDELEG_INSTRUCTION_PAGE_FAULT | MEDELEG_LOAD_PAGE_FAULT | MEDELEG_STORE_PAGE_FAULT);
csr_write(medeleg, MEDELEG_INSTRUCTION_PAGE_FAULT | MEDELEG_LOAD_PAGE_FAULT | MEDELEG_STORE_PAGE_FAULT | MEDELEG_USER_ENVIRONNEMENT_CALL);
csr_write(mideleg, MIDELEG_SUPERVISOR_TIMER);
csr_write(sbadaddr, 0); //Used to avoid simulation missmatch
}
@ -212,6 +212,10 @@ void trap(){
putC(a0);
csr_write(mepc, csr_read(mepc) + 4);
}break;
case SBI_CONSOLE_GETCHAR:{
writeRegister(10, -1); //no char
csr_write(mepc, csr_read(mepc) + 4);
}break;
case SBI_SET_TIMER:{
setMachineTimerCmp(a0, a1);
csr_set(mie, MIE_MTIE);

1
src/main/c/emulator/src/riscv.h
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@ -8,6 +8,7 @@
#define MEDELEG_INSTRUCTION_PAGE_FAULT (1 << 12)
#define MEDELEG_LOAD_PAGE_FAULT (1 << 13)
#define MEDELEG_STORE_PAGE_FAULT (1 << 15)
#define MEDELEG_USER_ENVIRONNEMENT_CALL (1 << 8)
#define MIDELEG_SUPERVISOR_TIMER (1 << 5)
#define MIE_MTIE (1 << 7)

4
src/main/scala/vexriscv/demo/Linux.scala
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@ -40,7 +40,7 @@ make run DBUS=SIMPLE IBUS=SIMPLE DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED
Run linux =>
sbt "runMain vexriscv.demo.LinuxGen"
cd src/test/cpp/regression
make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes LITEX=yes EMULATOR=/home/spinalvm/hdl/VexRiscv/src/main/c/emulator/build/emulator.bin VMLINUX=/home/spinalvm/hdl/linuxDave/vmlinux.bin DTB=/home/spinalvm/hdl/linuxDave/vmlinux/rv32.dtb RAMDISK=/home/spinalvm/hdl/linuxDave/initramdisk_dave TRACE=no
make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LITEX=yes EMULATOR=/home/spinalvm/hdl/VexRiscv/src/main/c/emulator/build/emulator.bin VMLINUX=/home/spinalvm/hdl/riscv-linux/vmlinux.bin DTB=/home/spinalvm/hdl/riscv-linux/rv32.dtb RAMDISK=/home/spinalvm/hdl/linuxDave/initramdisk_dave TRACE=yes0 FLOW_INFO=yes TRACE_START=9570000099
@ -51,7 +51,7 @@ riscv64-unknown-elf-objdump -S -d vmlinux > vmlinux.asm; split -b 1M vmlinux.asm
split -b 1M vmlinux.asm
dtc -O dtb -o rv32.dtb rv32.dts
make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes LITEX=yes EMULATOR=/home/spinalvm/hdl/VexRiscv/src/main/c/emulator/build/emulator.bin VMLINUX=/home/spinalvm/hdl/riscv-linux/vmlinux.bin DTB=/home/spinalvm/hdl/riscv-linux/rv32.dtb RAMDISK=/home/spinalvm/hdl/linuxDave/initramdisk_dave TRACE=yes FLOW_INFO=yes TRACE_START=0000000
make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LITEX=yes EMULATOR=/home/spinalvm/hdl/VexRiscv/src/main/c/emulator/build/emulator.bin VMLINUX=/home/spinalvm/hdl/riscv-linux/vmlinux.bin DTB=/home/spinalvm/hdl/riscv-linux/rv32.dtb RAMDISK=/home/spinalvm/hdl/linuxDave/initramdisk_dave TRACE=yes0 FLOW_INFO=yes TRACE_START=9570000099
*/

70
src/test/cpp/regression/main.cpp
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@ -835,7 +835,7 @@ public:
pcWrite(sepc);
}break;
case 0x00000073:{ //ECALL
trap(0, 8+privilege);
trap(0, 8+privilege, 0x00000073); //To follow the VexRiscv area saving implementation
}break;
case 0x10500073:{ //WFI
pcWrite(pc + 4);
@ -897,10 +897,10 @@ public:
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
bool hit = false;
for(int i = 0;i < RESERVED_ENTRY_COUNT;i++) hit |= reservedEntries[i].valid && reservedEntries[i].address == address;
rfWrite(rd32, !hit);
if(hit){
dWrite(pAddr, 4, i32_rs2);
}
rfWrite(rd32, !hit);
pcWrite(pc + 4);
}
} break;
@ -1063,6 +1063,7 @@ public:
ofstream regTraces;
ofstream memTraces;
ofstream logTraces;
ofstream debugLog;
struct timespec start_time;
@ -1125,6 +1126,9 @@ public:
if(ws->isPerifRegion(address)){
MemRead t = periphRead.front();
if(t.address != address || t.size != size){
cout << "DRead missmatch" << hex << endl;
cout << " REF : address=" << address << " size=" << size << endl;
cout << " DUT : address=" << t.address << " size=" << t.size << endl;
fail();
}
*data = t.data;
@ -1138,14 +1142,24 @@ public:
virtual void dWrite(int32_t address, int32_t size, uint32_t data){
if(address & (size-1) != 0)
cout << "Ref did a unaligned write" << endl;
if(ws->isPerifRegion(address)){
if(!ws->isPerifRegion(address)){
mem.write(address, size, (uint8_t*)&data);
}
if(ws->isDBusCheckedRegion(address)){
MemWrite w;
w.address = address;
w.size = size;
w.data = data;
switch(size){
case 1: w.data = data & 0xFF; break;
case 2: w.data = data & 0xFFFF; break;
case 4: w.data = data; break;
}
periphWritesGolden.push(w);
}else {
mem.write(address, size, (uint8_t*)&data);
if(periphWritesGolden.size() > 10){
cout << "??? periphWritesGolden" << endl;
fail();
}
}
}
@ -1193,6 +1207,7 @@ public:
memTraces.open (name + ".memTrace");hh
#endif
logTraces.open (name + ".logTrace");
debugLog.open (name + ".debugTrace");
fillSimELements();
clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time);
}
@ -1254,22 +1269,7 @@ public:
virtual bool isDBusCheckedRegion(uint32_t address){ return isPerifRegion(address);}
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
assertEq(addr % (1 << size), 0);
if(isPerifRegion(addr)){
if(wr){
CpuRef::MemWrite w;
w.address = addr;
w.size = 1 << size;
w.data = *data;
riscvRef.periphWrites.push(w);
} else {
CpuRef::MemRead r;
r.address = addr;
r.size = 1 << size;
r.data = *data;
r.error = *error;
riscvRef.periphRead.push(r);
}
} else {
if(!isPerifRegion(addr)) {
if(wr){
memTraces <<
#ifdef TRACE_WITH_TIME
@ -1305,6 +1305,30 @@ public:
}
}
if(wr){
if(isDBusCheckedRegion(addr)){
CpuRef::MemWrite w;
w.address = addr;
w.size = 1 << size;
switch(size){
case 0: w.data = *data & 0xFF; break;
case 1: w.data = *data & 0xFFFF; break;
case 2: w.data = *data ; break;
}
riscvRef.periphWrites.push(w);
}
} else {
if(isPerifRegion(addr)){
CpuRef::MemRead r;
r.address = addr;
r.size = 1 << size;
r.data = *data;
r.error = *error;
riscvRef.periphRead.push(r);
}
}
}
// void periphAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error){
@ -2946,7 +2970,7 @@ public:
LitexSoC(string name) : Workspace(name) {
}
virtual bool isDBusCheckedRegion(uint32_t address){ return true;}
virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xB0000000 || (addr & 0xE0000000) == 0xE0000000;}
virtual bool isMmuRegion(uint32_t addr) { return (addr & 0xFF000000) != 0x81000000;}