smp spec improvements, no more read abort
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Charles Papon
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@ -5,9 +5,11 @@ Features :
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- Two data paths (read + write), but allow dirty/clean sharing by reusing the write data path
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- Allow multi level coherent interconnect
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- No ordering, but provide barrier
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- Allow cache-full and cache-less agents
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## Memory copy status
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## Memory copy flags
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Memory copy, in other words, cache line, have more states than non coherent systems :
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| Name | Description |
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|---------------|-------------|
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@ -16,13 +18,14 @@ Features :
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| Owner/Lodger | lodger => copy of the line, but no other responsibility, owner => the given cache is responsible to write back dirty data and answer probes with the data |
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| Clean/Dirty | clean => match main memory, dirty => main memory need updates |
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All combination of those cache flag are valid. But if a cache line is invalid, the other flags have no meaning.
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All combination of those cache flag are valid. But if a cache line is invalid, the other status have no meaning.
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Later in the spec, memory copy state can be described as :
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Later in the spec, memory copy state can be described for example as :
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- VSOC for (Valid, Shared, Owner, Clean)
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- V-OC for (Valid, Shared or Unique, Owner, Clean)
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- !V-OC for NOT (Valid, Shared or Unique, Owner, Clean)
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- ...
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## buses
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@ -70,11 +73,11 @@ Emitted on the readCmd channel (master -> slave)
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| readShared | I--- | Get a memory copy as V--- | Want to read a uncached address |
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| readUnique | I--- | Get a memory copy as VUO- | Want to write a uncached address |
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| readOnce | I--- | Get a memory copy without coherency tracking | Instruction cache read |
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| makeInvalid | VS-- | Make other memory copy as I--- and make yourself VUO- | Want to write into a shared line |
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| makeUnique | VS-- | Make other memory copy as I--- and make yourself VUO- | Want to write into a shared line |
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| readBarrier | N/A | Ensure that the visibility of the memory operations of this channel do not cross the barrier | ISA fence |
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makeInvalid should be designed with care. There is a few corner cases :
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- While a master has a inflight makeInvalid, a probe can change its state.
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makeUnique should be designed with care. There is a few corner cases :
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- While a master has a inflight makeUnique, a probe can change its state, in such case, the makeUnique become weak and invalidation is canceled. This is usefull for multi level coherent interconnects.
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- Multi level coherent interconnect should be careful to properly move the ownership and not lose dirty data
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I'm not sure yet if we should add some barrier transactions to enforce
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@ -83,14 +86,13 @@ I'm not sure yet if we should add some barrier transactions to enforce
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Emitted on the readRsp channel (master <- slave)
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success, abort, error, data shared/unique clean/dirty owner/notOwner
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readSuccess, readError, data shared/unique clean/dirty owner/notOwner
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| Responses | From command | Description |
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|-----------|---------------|----------|
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| success | makeInvalid, readBarrier | - |
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| abort | makeInvalid | A concurrent makeInvalid toke over |
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| error | readShared, readUnique, readOnce | Bad address |
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| readData | readShared, readUnique, readOnce | Data + coherency flags (V???) |
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|-------------|---------------|----------|
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| readSuccess | makeUnique, readBarrier | - |
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| readError | readShared, readUnique, readOnce | Bad address |
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| readData | readShared, readUnique, readOnce | Data + coherency status (V???) |
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### Read ack
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@ -108,6 +110,7 @@ Write commands can be emitted on the writeCmd channel (master -> slave)
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|--------------|---------------|----------|----------|
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| writeInvalid | V-O- | Write the memory copy and update it status to I--- | Need to free the dirty cache line |
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| writeShare | V-O- | Write the memory copy but keep it as VSO- | A probe makeShared asked it |
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| writeUnique | VUO- | Write the memory copy but keep it as VUO- | A probe probeOnce need to read the data |
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| evict | V---, !V-OD | Notify the interconnect that the cache line is now I--- | Need to free a clean cache line |
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| writeBarrier | N/A | Ensure that the visibility of the memory operations of this channel do not cross the barrier | ISA fence |
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@ -127,8 +130,11 @@ Probe commands can be emitted on the probeCmd channel (slave -> master)
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|-------------|-------------|---------------|
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| makeInvalid | Make the memory copy I--- | Another cache want to make his shared copy unique to write it |
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| makeShared | Make the memory copy VS-- | Another cache want to read a memory block, so unique copy need to be shared |
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| probeOnce | Read the V-O- memory copy | A non coherent agent did a readOnce |
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Both makeInvalid and makeShared could result into one of the following probeSuccess, writeInvalid, writeShare.
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makeInvalid and makeShared could result into one of the following probeSuccess, writeInvalid, writeShare
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probeOnce can result into one of the following probeSuccess, writeShare, writeUnique
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To help the slave matching the writeInvalid and writeShare generated from a probe, those request are tagged with a matching ID.
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