XIP on Murax improvements
This commit is contained in:
sebastien-riou
parent
b290b25f7a
commit
b866dcb07f
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@ -1,19 +1,21 @@
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VBASE = ../../..
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VNAME = Murax_iCE40_hx8k_breakout_board_xip
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VERILOG = ${VBASE}/${VNAME}.v
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VERILOG = ../../../Murax_iCE40_hx8k_breakout_board_xip.v
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all: prog
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generate :
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#(cd ../../..; sbt "runMain vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip")
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${VERILOG} :
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(cd ${VBASE}; sbt "runMain vexriscv.demo.${VNAME}")
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../../../Murax_iCE40_hx8k_breakout_board_xip.v :
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#(cd ../../..; sbt "runMain vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip")
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generate : ${VERILOG}
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../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin:
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${VERILOG}*.bin:
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bin/Murax_iCE40_hx8k_breakout_board_xip.blif : ${VERILOG} ../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin
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bin/Murax_iCE40_hx8k_breakout_board_xip.blif : ${VERILOG} ${VERILOG}*.bin
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mkdir -p bin
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rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin
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cp ../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin . | true
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cp ${VERILOG}*.bin . | true
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yosys -v3 -p "synth_ice40 -top Murax_iCE40_hx8k_breakout_board_xip -blif bin/Murax_iCE40_hx8k_breakout_board_xip.blif" ${VERILOG}
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bin/Murax_iCE40_hx8k_breakout_board_xip.asc : Murax_iCE40_hx8k_breakout_board_xip.pcf bin/Murax_iCE40_hx8k_breakout_board_xip.blif
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@ -28,11 +30,15 @@ time: bin/Murax_iCE40_hx8k_breakout_board_xip.bin
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icetime -tmd hx8k bin/Murax_iCE40_hx8k_breakout_board_xip.asc
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prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin
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lsusb -d 0403:6010
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iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin
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sudo-prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin
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sudo lsusb -d 0403:6010
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sudo iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin
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clean :
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rm -rf bin
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rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin
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rm -f ${VERILOG}*.bin
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rm -f ${VERILOG}
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@ -59,12 +59,29 @@ The process should take around 30 seconds on a reasonable fast computer.
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## Programming
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Make sure the FPGA board is the only USB peripheral with ID 0403:6010
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For example, this is bad:
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```
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user@lafite:~$ lsusb -d 0403:6010
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Bus 001 Device 088: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC
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Bus 001 Device 090: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC
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```
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This is good:
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```
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user@lafite:~$ lsusb -d 0403:6010
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Bus 001 Device 088: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC
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```
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After building you should be able to run `make prog`. You may need to run `make
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sudo-prog` if root is needed to access your USB devices.
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You should get output like the following;
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```
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iceprog -S bin/toplevel.bin
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lsusb -d 0403:6010
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Bus 001 Device 088: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC
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iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin
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init..
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cdone: high
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reset..
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@ -74,13 +91,115 @@ cdone: high
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Bye.
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```
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After programming the LEDs at the top of the board should start flashing in an
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interesting pattern.
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WARNING: having this output does NOT guarantee you actually programmed anything in the FPGA!
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## Connect
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After programming nothing visual will happen, except the LEDs being off.
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The bootloader is waiting for a valid content in the flash. "valid content" is
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identified by a magic word at 0xE0040000: it shall be 0x12340fb7, which is the
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value for the instruction "li x31, 0x12340000".
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After programming you should be able to connect to the serial port and have the
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output echoed back to you.
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## Programming flash image
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On Linux you can do this using a command like `screen /dev/ttyUSB1`. Then as
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you type you should get back the same characters.
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### Connect JTAG
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We will use vexrisc JTAG to program the flash, so you need openocd and a
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suitable JTAG dongle.
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Pin-out:
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```
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TCK: H16 aka J2.25
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TDO: G16 aka J2.26
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TDI: G15 aka J2.27
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TMS: F15 aka J2.28
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```
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In addition you need to connect the ground and VTarget aka VIO: J2.2 on the
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board.
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### Start GDB server / OpenOCD
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Make sure to use https://github.com/SpinalHDL/openocd_riscv
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Make sure to select the configuration file which match your JTAG dongle.
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An example with the dongle "ft2232h_breakout":
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```
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src/openocd -f tcl/interface/ftdi/ft2232h_breakout.cfg -c "set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml" -f tcl/target/murax_xip.cfg
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```
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You should get an output like below:
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```
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Open On-Chip Debugger 0.10.0+dev-01214-g0ace94f (2019-10-02-18:23)
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Licensed under GNU GPL v2
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For bug reports, read
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http://openocd.org/doc/doxygen/bugs.html
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../VexRiscv/cpu0.yaml
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adapter speed: 100 kHz
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adapter_nsrst_delay: 260
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Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
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jtag_ntrst_delay: 250
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Info : set servers polling period to 50ms
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Error: libusb_get_string_descriptor_ascii() failed with LIBUSB_ERROR_INVALID_PARAM
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Info : clock speed 100 kHz
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Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
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Info : Listening on port 3333 for gdb connections
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requesting target halt and executing a soft reset
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Info : Listening on port 6666 for tcl connections
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Info : Listening on port 4444 for telnet connections
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```
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### Loading the flash with telnet
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First we connect and stop execution on the device:
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```
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user@lafite:~/Downloads/vexrisc_full/VexRiscv/src/main/c/murax/xipBootloader$ telnet 127.0.0.1 4444
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Trying 127.0.0.1...
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Connected to 127.0.0.1.
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Escape character is '^]'.
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Open On-Chip Debugger
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> reset
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JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
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>
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```
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Now we can safely connect the J7 jumper on the board to be able to access the flash.
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After that, we can load the program in flash:
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```
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> flash erase_sector 0 4 4
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erased sectors 4 through 4 on flash bank 0 in 0.872235s
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> flash write_bank 0 /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin 0x40000
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wrote 48 bytes from file /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin to flash bank 0 at offset 0x00040000 in 0.285539s (0.164 KiB/s)
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> flash verify_bank 0 /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin 0x40000
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read 48 bytes from file /home/user/dev/vexrisc_fork/VexRiscv/src/main/c/murax/xipBootloader/demo_xip.bin and flash bank 0 at offset 0x00040000 in 0.192036s (0.244 KiB/s)
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contents match
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> reset
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JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
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> resume
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> exit
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Connection closed by foreign host.
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```
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From now the device runs the code from flash, LEDs shall display a dot moving from D9 to D2.
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### Loading flash using GDB / eclipse
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- ```
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src/openocd -f tcl/interface/ftdi/ft2232h_breakout.cfg -c "set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml" -f tcl/target/murax_xip.cfg
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```
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- Make sure J7 is connected.
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- Connect to GDB / eclipse as usual.
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From there code loading, step, break points works as usual (including software break points in flash).
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## Update hardware/bootloader
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- Stop any OpenOCD connection
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- Remove J7, then:
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- ```
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make clean prog
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```
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- Remember to check a single FTDI device is listed in the output. If not:
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- Disconnect the other devices
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- ```
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make prog
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```
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- Connect J7, flash software shall start executing.
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## Flash software
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Refer to "Loading the flash with telnet" or "Loading flash using GDB / eclipse".
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@ -42,13 +42,25 @@ crtStart:
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li t0, 0x1
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sw t0, CTRL_XIP_CONFIG(CTRL)
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li t0, XIP_BASE
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lw t1, (t0)
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li t2, 0x12340fb7
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xor t1,t1,t2
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bnez t1,retry
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jr t0
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retry:
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li a0, 0x800
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call spiWrite
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li t1,100000
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loop:
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addi t1,t1,-1
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bnez t1, loop
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j crtStart
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spiWrite:
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sw a0,CTRL_DATA(CTRL)
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spiWrite_wait:
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lw t0,CTRL_STATUS(CTRL)
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srli t0,t0,0x10
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slli t0,t0,0x10
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beqz t0,spiWrite_wait
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ret
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Binary file not shown.
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@ -7,18 +7,21 @@
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crtStart:
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li x31, 0x12340000 // magic word expected by bootloader
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li x31, GPIO_BASE
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li t0, 0x000000FF
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sw t0, GPIO_OUTPUT_ENABLE(x31)
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li t0,0
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li t0,1
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redo:
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sw t0, GPIO_OUTPUT(x31)
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li t1,10000
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addi t0,t0,1
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slli t0,t0,1
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andi t0,t0,0xFF
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bnez t0, loop
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li t0,1
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loop:
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addi t1,t1,-1
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bnez t1, loop
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j redo
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Binary file not shown.
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@ -4,20 +4,34 @@ LFLAGS= -nostdlib -mcmodel=medany -nostartfiles -ffreestanding -fPIC -fPIE
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all: crt.S demo.S
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riscv64-unknown-elf-gcc -c $(CFLAGS) -o crt.o crt.S
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riscv64-unknown-elf-gcc $(CFLAGS) -o crt.elf crt.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,crt.map,--print-memory-usage
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riscv64-unknown-elf-gcc $(CFLAGS) -o crt.elf crt.o $(LFLAGS) -Wl,-Bstatic,-T,mapping_rom.ld,-Map,crt.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d crt.elf > crt.asm
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riscv64-unknown-elf-objcopy -O binary crt.elf crt.bin
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riscv64-unknown-elf-gcc $(CFLAGS) -o crt_ram.elf crt.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,crt_ram.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d crt_ram.elf > crt_ram.asm
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riscv64-unknown-elf-objcopy -O binary crt_ram.elf crt_ram.bin
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riscv64-unknown-elf-gcc -c $(CFLAGS) -o demo.o demo.S
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riscv64-unknown-elf-gcc $(CFLAGS) -o demo.elf demo.o $(LFLAGS) -Wl,-Bstatic,-T,mapping.ld,-Map,demo.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d demo.elf > demo.asm
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riscv64-unknown-elf-objcopy -O binary demo.elf demo.bin
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riscv64-unknown-elf-gcc $(CFLAGS) -o demo_rom.elf demo.o $(LFLAGS) -Wl,-Bstatic,-T,mapping_rom.ld,-Map,demo_rom.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d demo_rom.elf > demo_rom.asm
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riscv64-unknown-elf-objcopy -O binary demo_rom.elf demo_rom.bin
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riscv64-unknown-elf-gcc $(CFLAGS) -o demo_xip.elf demo.o $(LFLAGS) -Wl,-Bstatic,-T,mapping_xip.ld,-Map,demo_xip.map,--print-memory-usage
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riscv64-unknown-elf-objdump -S -d demo_xip.elf > demo_xip.asm
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riscv64-unknown-elf-objcopy -O binary demo_xip.elf demo_xip.bin
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clean:
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clean-for-commit:
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rm -f *.o
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rm -f *.bin
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rm -f *.elf
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rm -f *.asm
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rm -f *.map
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rm -f *.d
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rm demo_rom.bin demo.bin crt_ram.bin
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clean: clean-tmp
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rm -f *.bin
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@ -0,0 +1,96 @@
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/*
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This is free and unencumbered software released into the public domain.
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Anyone is free to copy, modify, publish, use, compile, sell, or
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distribute this software, either in source code form or as a compiled
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binary, for any purpose, commercial or non-commercial, and by any
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means.
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*/
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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ENTRY(crtStart)
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MEMORY {
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mem : ORIGIN = 0x80000000, LENGTH = 0x00000400
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rom : ORIGIN = 0xF001E000, LENGTH = 0x00000400
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}
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_stack_size = DEFINED(_stack_size) ? _stack_size : 0;
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SECTIONS {
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.vector : {
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*crt.o(.text);
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} > rom
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.memory : {
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*(.text);
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end = .;
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} > rom
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.rodata :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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} > rom
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.ctors :
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{
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. = ALIGN(4);
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_ctors_start = .;
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KEEP(*(.init_array*))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(4);
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_ctors_end = .;
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} > rom
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.data :
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{
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*(.rdata)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.r.*)
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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. = ALIGN(8);
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PROVIDE( __global_pointer$ = . + 0x800 );
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*(.sdata .sdata.*)
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*(.gnu.linkonce.s.*)
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. = ALIGN(8);
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*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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} > rom
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.bss (NOLOAD) : {
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_bss_start = .;
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*(.sbss*)
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*(.gnu.linkonce.sb.*)
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_bss_end = .;
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} > mem
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.noinit (NOLOAD) : {
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. = ALIGN(4);
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*(.noinit .noinit.*)
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. = ALIGN(4);
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} > mem
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._stack (NOLOAD):
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{
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. = ALIGN(16);
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PROVIDE (_stack_end = .);
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. = . + _stack_size;
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. = ALIGN(16);
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PROVIDE (_stack_start = .);
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} > mem
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}
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@ -0,0 +1,96 @@
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/*
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This is free and unencumbered software released into the public domain.
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|
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Anyone is free to copy, modify, publish, use, compile, sell, or
|
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distribute this software, either in source code form or as a compiled
|
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binary, for any purpose, commercial or non-commercial, and by any
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means.
|
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*/
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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ENTRY(crtStart)
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MEMORY {
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mem : ORIGIN = 0x80000000, LENGTH = 0x00000400
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xip : ORIGIN = 0xE0040000, LENGTH = 0x00000400
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}
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_stack_size = DEFINED(_stack_size) ? _stack_size : 0;
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SECTIONS {
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.vector : {
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*crt.o(.text);
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} > xip
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|
||||
.memory : {
|
||||
*(.text);
|
||||
end = .;
|
||||
} > xip
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} > xip
|
||||
|
||||
.ctors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_ctors_start = .;
|
||||
KEEP(*(.init_array*))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
. = ALIGN(4);
|
||||
_ctors_end = .;
|
||||
} > xip
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} > xip
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_bss_start = .;
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_bss_end = .;
|
||||
} > mem
|
||||
|
||||
.noinit (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
*(.noinit .noinit.*)
|
||||
. = ALIGN(4);
|
||||
} > mem
|
||||
|
||||
._stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(16);
|
||||
PROVIDE (_stack_end = .);
|
||||
. = . + _stack_size;
|
||||
. = ALIGN(16);
|
||||
PROVIDE (_stack_start = .);
|
||||
} > mem
|
||||
|
||||
}
|
||||
|
|
@ -385,7 +385,8 @@ object Murax_iCE40_hx8k_breakout_board_xip{
|
|||
|
||||
val led = out Bits(8 bits)
|
||||
}
|
||||
val murax = Murax(MuraxConfig.default(withXip = true))
|
||||
//val murax = Murax(MuraxConfig.default(withXip = true))
|
||||
val murax = Murax(MuraxConfig.default(withXip = true).copy(onChipRamSize = 8 kB))
|
||||
murax.io.asyncReset := False
|
||||
|
||||
val mainClkBuffer = SB_GB()
|
||||
|
|
@ -438,45 +439,6 @@ object Murax_iCE40_hx8k_breakout_board_xip{
|
|||
|
||||
def main(args: Array[String]) {
|
||||
SpinalVerilog(Murax_iCE40_hx8k_breakout_board_xip())
|
||||
/*SpinalVerilog{
|
||||
val c = Murax(MuraxConfig.default(withXip = true))
|
||||
|
||||
|
||||
|
||||
|
||||
c.rework {
|
||||
c.resetCtrlClockDomain {
|
||||
c.io.xip.setAsDirectionLess.allowDirectionLessIo.flattenForeach(_.unsetName())
|
||||
|
||||
out(RegNext(c.io.xip.ss)).setName("io_xip_ss")
|
||||
|
||||
val sclk = SB_IO_SCLK()
|
||||
sclk.PACKAGE_PIN := inout(Analog(Bool)).setName("io_xip_sclk")
|
||||
sclk.CLOCK_ENABLE := True
|
||||
|
||||
sclk.OUTPUT_CLK := ClockDomain.current.readClockWire
|
||||
sclk.D_OUT_0 <> c.io.xip.sclk.write(0)
|
||||
sclk.D_OUT_1 <> RegNext(c.io.xip.sclk.write(1))
|
||||
|
||||
for (i <- 0 until c.io.xip.p.dataWidth) {
|
||||
val data = c.io.xip.data(i)
|
||||
val bb = SB_IO_DATA()
|
||||
bb.PACKAGE_PIN := inout(Analog(Bool)).setName(s"io_xip_data_$i" )
|
||||
bb.CLOCK_ENABLE := True
|
||||
|
||||
bb.OUTPUT_CLK := ClockDomain.current.readClockWire
|
||||
bb.OUTPUT_ENABLE <> data.writeEnable
|
||||
bb.D_OUT_0 <> data.write(0)
|
||||
bb.D_OUT_1 <> RegNext(data.write(1))
|
||||
|
||||
bb.INPUT_CLK := ClockDomain.current.readClockWire
|
||||
data.read(0) := bb.D_IN_0
|
||||
data.read(1) := RegNext(bb.D_IN_1)
|
||||
}
|
||||
}
|
||||
}
|
||||
c
|
||||
}*/
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue