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VexRiscv
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Two stage datacache now pass dhrystone benchmark without error

This commit is contained in:
Charles Papon 2017-04-23 23:15:38 +02:00
parent 9040326273
commit ba2ca77114
7 changed files with 176169 additions and 133 deletions
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12
src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala
View File

@ -612,18 +612,22 @@ class DataCache(p : DataCacheConfig) extends Component{
// }
is(MEMORY) {
when(request.bypass) {
val memCmdSent = RegInit(False)
when(!victim.request.valid) { //Avoid mixing memory request while victim is pending
//Can't+rite burst
val memCmdValid = RegInit(False) clearWhen(io.mem.cmd.ready) setWhen(!io.cpu.writeBack.isStuck)
io.mem.cmd.valid := memCmdValid
io.mem.cmd.wr := request.wr
io.mem.cmd.address := request.address(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit)
io.mem.cmd.mask := request.mask
io.mem.cmd.data := request.data
io.mem.cmd.length := 1
io.cpu.writeBack.haltIt.clearWhen(io.mem.rsp.fire || (!memCmdValid && request.wr)) //Cut mem.cmd.ready path but insert one cycle stall when write
when(!memCmdSent) {
io.mem.cmd.valid := True
memCmdSent setWhen(io.mem.cmd.ready)
}
io.cpu.writeBack.haltIt.clearWhen(memCmdSent && (io.mem.rsp.fire || request.wr)) //Cut mem.cmd.ready path but insert one cycle stall when write
}
memCmdSent clearWhen(!io.cpu.writeBack.isStuck)
} otherwise {
when(waysHit || !loadingNotDone){
io.cpu.writeBack.haltIt := False

122
src/main/scala/SpinalRiscv/TopLevel.scala
View File

@ -79,39 +79,39 @@ object TopLevel {
configFull.plugins ++= List(
new PcManagerSimplePlugin(0x00000000l, false),
// new IBusSimplePlugin(
// interfaceKeepData = true,
// catchAccessFault = true
// ),
new IBusCachedPlugin(
config = InstructionCacheConfig(
cacheSize = 4096,
bytePerLine =32,
wayCount = 1,
wrappedMemAccess = true,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = true,
asyncTagMemory = false,
twoStageLogic = true
)
),
new DBusSimplePlugin(
catchAddressMisaligned = true,
new IBusSimplePlugin(
interfaceKeepData = true,
catchAccessFault = true
),
// new DBusCachedPlugin(
// config = new DataCacheConfig(
// new IBusCachedPlugin(
// config = InstructionCacheConfig(
// cacheSize = 4096,
// bytePerLine =32,
// wayCount = 1,
// wrappedMemAccess = true,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessFault = false
// catchAccessFault = true,
// asyncTagMemory = false,
// twoStageLogic = true
// )
// ),
// new DBusSimplePlugin(
// catchAddressMisaligned = true,
// catchAccessFault = true
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = false
)
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
),
@ -176,15 +176,16 @@ object TopLevel {
new LightShifterPlugin,
// new HazardSimplePlugin(true, true, true, true),
// new HazardSimplePlugin(false, true, false, true),
new HazardSimplePlugin(
bypassExecute = false,
bypassMemory = false,
bypassWriteBack = false,
bypassWriteBackBuffer = false,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
// new HazardSimplePlugin(
// bypassExecute = false,
// bypassMemory = false,
// bypassWriteBack = false,
// bypassWriteBackBuffer = false,
// pessimisticUseSrc = false,
// pessimisticWriteRegFile = false,
// pessimisticAddressMatch = false
// ),
new HazardPessimisticPlugin,
// new MulPlugin,
// new DivPlugin,
// new MachineCsr(csrConfig),
@ -202,29 +203,29 @@ object TopLevel {
configTest.plugins ++= List(
new PcManagerSimplePlugin(0x00000000l, true),
// new IBusSimplePlugin(
// interfaceKeepData = true,
// catchAccessFault = false
// ),
new IBusCachedPlugin(
config = InstructionCacheConfig(
cacheSize = 4096,
bytePerLine =32,
wayCount = 1,
wrappedMemAccess = true,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = false,
asyncTagMemory = false,
twoStageLogic = true
)
),
new DBusSimplePlugin(
catchAddressMisaligned = false,
new IBusSimplePlugin(
interfaceKeepData = true,
catchAccessFault = false
),
// new IBusCachedPlugin(
// config = InstructionCacheConfig(
// cacheSize = 4096,
// bytePerLine =32,
// wayCount = 1,
// wrappedMemAccess = true,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessFault = false,
// asyncTagMemory = false,
// twoStageLogic = true
// )
// ),
// new DBusSimplePlugin(
// catchAddressMisaligned = false,
// catchAccessFault = false
// ),
// new DBusCachedPlugin(
// config = new DataCacheConfig(
// cacheSize = 2048,
@ -236,13 +237,23 @@ object TopLevel {
// catchAccessFault = false
// )
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 128,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = false
)
),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = Plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
@ -291,3 +302,4 @@ object TopLevel {
//TODO MulPlugin doesn't fit well on Artix (FMAX)
//TODO PcReg design is unoptimized by Artix synthesis
//TODO FMAX SRC mux + bipass mux prioriti
//TODO FMAX, isFiring is to pesimisstinc in some cases(include removeIt flushed ..)

57066
src/test/cpp/testA/dhrystoneO3_Stall.memRef Normal file
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File diff suppressed because it is too large Load Diff

118919
src/test/cpp/testA/dhrystoneO3_Stall.regRef Normal file
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File diff suppressed because it is too large Load Diff

149
src/test/cpp/testA/fail.gtkw
View File

@ -1,85 +1,110 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Wed Apr 12 17:13:59 2017
[*] Sun Apr 23 20:40:44 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3.vcd"
[dumpfile_mtime] "Wed Apr 12 17:05:50 2017"
[dumpfile_size] 476292557
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3_Stall.vcd"
[dumpfile_mtime] "Sun Apr 23 20:39:06 2017"
[dumpfile_size] 524533821
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/fail.gtkw"
[timestart] 602234
[timestart] 122461
[size] 1776 953
[pos] -775 -1
*-3.626630 602285 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -775 -353
*-7.000000 122712 59602 124439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.VexRiscv.
[sst_width] 201
[signals_width] 518
[signals_width] 565
[sst_expanded] 1
[sst_vpaned_height] 279
@22
TOP.VexRiscv.instructionCache_1.io_cpu_prefetch_address[31:0]
[sst_vpaned_height] 253
@28
TOP.VexRiscv.instructionCache_1.io_cpu_prefetch_haltIt
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.writeBack_arbitration_isFiring
@22
TOP.VexRiscv.writeBack_PC[31:0]
TOP.VexRiscv.writeBack_INSTRUCTION[31:0]
@28
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
@22
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
@28
TOP.VexRiscv.execute_arbitration_isValid
TOP.VexRiscv.execute_arbitration_isStuck
@22
TOP.VexRiscv.execute_PC[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr
@800200
-Fetch
@22
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_address[31:0]
@28
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isStuck
TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isValid
@1000200
-Fetch
@800200
-Decode
@22
TOP.VexRiscv.instructionCache_1.io_cpu_decode_address[31:0]
TOP.VexRiscv.instructionCache_1.io_cpu_decode_data[31:0]
@28
TOP.VexRiscv.instructionCache_1.io_cpu_decode_haltIt
TOP.VexRiscv.instructionCache_1.io_cpu_decode_isStuck
TOP.VexRiscv.instructionCache_1.io_cpu_decode_isValid
@1000200
-Decode
@800200
-Task
@22
TOP.VexRiscv.instructionCache_1.task_memRead_data[31:0]
TOP.VexRiscv.instructionCache_1.task_memRead_tag_address[19:0]
@28
TOP.VexRiscv.instructionCache_1.task_memRead_tag_valid
@22
TOP.VexRiscv.instructionCache_1.task_tag_address[19:0]
@28
TOP.VexRiscv.instructionCache_1.task_tag_valid
@22
TOP.VexRiscv.instructionCache_1.task_dataRegIn[31:0]
TOP.VexRiscv.instructionCache_1.task_data[31:0]
-execute
@29
TOP.VexRiscv.instructionCache_1.task_cacheHit
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0]
@28
TOP.VexRiscv.instructionCache_1.task_hit
TOP.VexRiscv.instructionCache_1.task_loaderHit
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_all
@29
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_bypass
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_kind[1:0]
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_mask[3:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr
TOP.VexRiscv.dataCache_1.io_cpu_execute_isStuck
@1000200
-Task
@22
TOP.VexRiscv.instructionCache_1.io_mem_cmd_payload_address[31:0]
-execute
@28
TOP.VexRiscv.instructionCache_1.io_mem_cmd_ready
TOP.VexRiscv.instructionCache_1.io_mem_cmd_valid
TOP.VexRiscv.dataCache_1.io_cpu_memory_isStuck
@800200
-writeBack
@22
TOP.VexRiscv.instructionCache_1.io_mem_rsp_payload_data[31:0]
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_data[31:0]
@28
TOP.VexRiscv.instructionCache_1.io_mem_rsp_valid
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_haltIt
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_isStuck
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_isValid
@1000200
-writeBack
@28
TOP.VexRiscv.dataCache_1.io_mem_cmd_valid
TOP.VexRiscv.dataCache_1.io_mem_cmd_ready
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_wr
@22
TOP.VexRiscv.instructionCache_1.lineLoader_waysDatasWritePort_payload_address[9:0]
TOP.VexRiscv.instructionCache_1.lineLoader_waysDatasWritePort_payload_data[31:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_address[31:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_data[31:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_mask[3:0]
TOP.VexRiscv.dataCache_1.io_mem_rsp_payload_data[31:0]
@28
TOP.VexRiscv.instructionCache_1.lineLoader_waysDatasWritePort_valid
TOP.VexRiscv.clk
TOP.VexRiscv.dataCache_1.io_mem_rsp_valid
@22
TOP.VexRiscv.instructionCache_1.lineLoader_request_payload_addr[31:0]
TOP.VexRiscv.dataCache_1.dataWriteCmd_payload_data[31:0]
TOP.VexRiscv.dataCache_1.dataWriteCmd_payload_mask[3:0]
@28
TOP.VexRiscv.instructionCache_1.lineLoader_request_ready
TOP.VexRiscv.instructionCache_1.lineLoader_request_valid
TOP.VexRiscv.dataCache_1.dataWriteCmd_valid
TOP.VexRiscv.dataCache_1.clk
TOP.VexRiscv.dataCache_1.way_dataReadRspTwoEnable
@22
TOP.VexRiscv.dataCache_1.way_dataReadRspTwo[31:0]
@28
TOP.VexRiscv.dataCache_1.way_tagReadRspTwoEnable
TOP.VexRiscv.dataCache_1.way_tagReadRspTwo_dirty
TOP.VexRiscv.dataCache_1.way_tagReadRspTwo_used
@22
TOP.VexRiscv.dataCache_1.way_dataReadRspOne[31:0]
@28
TOP.VexRiscv.dataCache_1.victim_request_ready
TOP.VexRiscv.dataCache_1.victim_request_valid
TOP.VexRiscv.dataCache_1.victim_dataReadRestored
@22
TOP.VexRiscv.dataCache_1.victim_readLineCmdCounter[3:0]
TOP.VexRiscv.dataCache_1.dataReadCmd_payload[4:0]
@28
TOP.VexRiscv.dataCache_1.dataReadCmd_valid
[pattern_trace] 1
[pattern_trace] 0

7
src/test/cpp/testA/main.cpp
View File

@ -239,7 +239,10 @@ public:
}
switch(addr){
case 0xF00FFF10u:
*data = i/2;
*data = mTime;
#ifdef REF_TIME
mTime += 100000;
#endif
break;
case 0xF00FFF40u: *data = mTime; break;
case 0xF00FFF44u: *data = mTime >> 32; break;
@ -309,7 +312,9 @@ public:
try {
// run simulation for 100 clock periods
for (i = 16; i < timeout*2; i+=2) {
#ifndef REF_TIME
mTime = i/2;
#endif
#ifdef CSR
top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0;
//if(mTime == mTimeCmp) printf("SIM timer tick\n");

11
src/test/cpp/testA/makefile
View File

@ -1,13 +1,14 @@
IBUS=IBUS_CACHED
DBUS=DBUS_SIMPLE
IBUS=IBUS_SIMPLE
DBUS=DBUS_CACHED
TRACE=no
TRACE_START=0
CSR=yes
CSR=no
DHRYSTONE=yes
FREE_RTOS=no
REDO=10
REF=no
TRACE_WITH_TIME=no
REF_TIME=no
ADDCFLAGS += -CFLAGS -D${IBUS}
ADDCFLAGS += -CFLAGS -D${DBUS}
@ -29,6 +30,10 @@ ifeq ($(TRACE_WITH_TIME),yes)
ADDCFLAGS += -CFLAGS -DTRACE_WITH_TIME
endif
ifeq ($(REF_TIME),yes)
ADDCFLAGS += -CFLAGS -DREF_TIME
endif
ifeq ($(REF),yes)
ADDCFLAGS += -CFLAGS -DREF
endif