pass VexRiscv regressions
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173336af33
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@ -9,7 +9,7 @@ scalaVersion := "2.11.8"
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EclipseKeys.withSource := true
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libraryDependencies ++= Seq(
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.10.15",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.10.15",
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.0",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.0",
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"org.yaml" % "snakeyaml" % "1.8"
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)
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@ -12,13 +12,12 @@ class Stageable[T <: Data](val dataType : T) extends HardType[T](dataType) with
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class Stage() extends Area{
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def outsideCondScope[T](that : => T) : T = {
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val condStack = GlobalData.get.conditionalAssignStack.stack.toList
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val switchStack = GlobalData.get.switchStack.stack.toList
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GlobalData.get.conditionalAssignStack.stack.clear()
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GlobalData.get.switchStack.stack.clear()
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val body = Component.current.dslBody
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body.push()
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val swapContext = body.swap()
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val ret = that
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GlobalData.get.conditionalAssignStack.stack.pushAll(condStack.reverseIterator)
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GlobalData.get.switchStack.stack.pushAll(switchStack.reverseIterator)
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body.pop()
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swapContext.appendBack()
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ret
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}
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@ -28,7 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
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object TestsWorkspace {
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def main(args: Array[String]) {
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SpinalVerilog {
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SpinalConfig(mergeAsyncProcess = false).generateVerilog {
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val configFull = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(
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@ -54,5 +54,5 @@ object GenSmallestNoCsr extends App{
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)
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)
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)
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SpinalVerilog(cpu())
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SpinalConfig(mergeAsyncProcess = false).generateVerilog(cpu())
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}
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@ -83,11 +83,11 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
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stageables.foreach(e => {
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defaults.get(e) match {
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case Some(value) => {
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value.input match {
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value.head.source match {
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case literal: EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
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case _ =>
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}
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defaultValue += value.input.asInstanceOf[Literal].getValue << offset
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defaultValue += value.head.source .asInstanceOf[Literal].getValue << offset
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defaultCare += ((BigInt(1) << e.dataType.getBitsWidth) - 1) << offset
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}
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@ -102,12 +102,12 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
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var decodedValue = defaultValue
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var decodedCare = defaultCare
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for((e, literal) <- values){
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literal.input match{
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literal.head.source match{
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case literal : EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
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case _ =>
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}
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val offset = offsetOf(e)
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decodedValue |= literal.input.asInstanceOf[Literal].getValue << offset
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decodedValue |= literal.head.source.asInstanceOf[Literal].getValue << offset
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decodedCare |= ((BigInt(1) << e.dataType.getBitsWidth)-1) << offset
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}
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(Masked(key.value,key.careAbout),Masked(decodedValue,decodedCare))
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@ -145,7 +145,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
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val stageables = encodings.flatMap(_._2.map(_._1)).toSet
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stageables.foreach(e => out(RegNext(RegNext(toplevel.decode.insert(e)).setName(e.getName()))))
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if(catchIllegalInstruction) out(RegNext(RegNext(toplevel.decode.insert(LEGAL_INSTRUCTION)).setName(LEGAL_INSTRUCTION.getName())))
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toplevel.getAdditionalNodesRoot.clear()
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// toplevel.getAdditionalNodesRoot.clear()
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}
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}
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}
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