Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

fix too early

Browse source 
# Conflicts:
#	src/main/scala/vexriscv/demo/SynthesisBench.scala
This commit is contained in:
Dolu1990 2023-02-19 09:51:18 +01:00
parent 1c38b6ec66
commit bbbfc7ee6b
1 changed files with 66 additions and 74 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

46
src/main/scala/vexriscv/demo/SynthesisBench.scala
View file

@ -409,9 +409,11 @@ object VexRiscvCustomSynthesisBench {
def main(args: Array[String]) { def main(args: Array[String]) {
def gen(csr : CsrPlugin) = new VexRiscv( def gen(csr : CsrPlugin, p : Plugin[VexRiscv]) = {
val cpu = new VexRiscv(
config = VexRiscvConfig( config = VexRiscvConfig(
plugins = List( plugins = List(
p,
new IBusSimplePlugin( new IBusSimplePlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
cmdForkOnSecondStage = false, cmdForkOnSecondStage = false,
@ -455,42 +457,32 @@ object VexRiscvCustomSynthesisBench {
) )
) )
) )
cpu.rework {
for (plugin <- cpu.config.plugins) plugin match {
val fixedMtvec = new Rtl { case plugin: DebugPlugin => plugin.debugClockDomain {
override def getName(): String = "Fixed MTVEC" plugin.io.bus.setAsDirectionLess()
override def getRtlPath(): String = "fixedMtvec.v" val jtag = slave(new Jtag())
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l))).setDefinitionName(getRtlPath().split("\\.").head)) .setName("jtag")
jtag <> plugin.io.bus.fromJtag()
} }
case _ =>
val writeOnlyMtvec = new Rtl {
override def getName(): String = "write only MTVEC"
override def getRtlPath(): String = "woMtvec.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = WRITE_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
} }
val readWriteMtvec = new Rtl {
override def getName(): String = "read write MTVEC"
override def getRtlPath(): String = "wrMtvec.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE))).setDefinitionName(getRtlPath().split("\\.").head))
} }
cpu
val fixedMtvecRoCounter = new Rtl {
override def getName(): String = "Fixed MTVEC, read only mcycle/minstret"
override def getRtlPath(): String = "fixedMtvecRoCounter.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
} }
val rwMtvecRoCounter = new Rtl { val vexDebug = new Rtl {
override def getName(): String = "read write MTVEC, read only mcycle/minstret" override def getName(): String = "vexDebug"
override def getRtlPath(): String = "readWriteMtvecRoCounter.v" override def getRtlPath(): String = "vexDebug.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE, mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l)),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset")))
).setDefinitionName(getRtlPath().split("\\.").head))
} }
// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp) // val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
val rtls = List(fixedMtvec, writeOnlyMtvec, readWriteMtvec,fixedMtvecRoCounter, rwMtvecRoCounter) val rtls = List(vexDebug)
// val rtls = List(smallest) // val rtls = List(smallest)
val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1)