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fix too early

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# Conflicts:
#	src/main/scala/vexriscv/demo/SynthesisBench.scala
This commit is contained in:
Dolu1990 2023-02-19 09:51:18 +01:00
parent 1c38b6ec66
commit bbbfc7ee6b
1 changed files with 66 additions and 74 deletions
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138
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -409,88 +409,80 @@ object VexRiscvCustomSynthesisBench {
def main(args: Array[String]) { def main(args: Array[String]) {
def gen(csr : CsrPlugin) = new VexRiscv( def gen(csr : CsrPlugin, p : Plugin[VexRiscv]) = {
config = VexRiscvConfig( val cpu = new VexRiscv(
plugins = List( config = VexRiscvConfig(
new IBusSimplePlugin( plugins = List(
resetVector = 0x80000000l, p,
cmdForkOnSecondStage = false, new IBusSimplePlugin(
cmdForkPersistence = false, resetVector = 0x80000000l,
prediction = NONE, cmdForkOnSecondStage = false,
catchAccessFault = false, cmdForkPersistence = false,
compressedGen = false prediction = NONE,
), catchAccessFault = false,
new DBusSimplePlugin( compressedGen = false
catchAddressMisaligned = false, ),
catchAccessFault = false new DBusSimplePlugin(
), catchAddressMisaligned = false,
new DecoderSimplePlugin( catchAccessFault = false
catchIllegalInstruction = false ),
), new DecoderSimplePlugin(
new RegFilePlugin( catchIllegalInstruction = false
regFileReadyKind = plugin.SYNC, ),
zeroBoot = false new RegFilePlugin(
), regFileReadyKind = plugin.SYNC,
new IntAluPlugin, zeroBoot = false
new SrcPlugin( ),
separatedAddSub = false, new IntAluPlugin,
executeInsertion = true new SrcPlugin(
), separatedAddSub = false,
csr, executeInsertion = true
new FullBarrelShifterPlugin(), ),
new HazardSimplePlugin( csr,
bypassExecute = true, new FullBarrelShifterPlugin(),
bypassMemory = true, new HazardSimplePlugin(
bypassWriteBack = true, bypassExecute = true,
bypassWriteBackBuffer = true, bypassMemory = true,
pessimisticUseSrc = false, bypassWriteBack = true,
pessimisticWriteRegFile = false, bypassWriteBackBuffer = true,
pessimisticAddressMatch = false pessimisticUseSrc = false,
), pessimisticWriteRegFile = false,
new BranchPlugin( pessimisticAddressMatch = false
earlyBranch = false, ),
catchAddressMisaligned = false new BranchPlugin(
), earlyBranch = false,
new YamlPlugin("cpu0.yaml") catchAddressMisaligned = false
),
new YamlPlugin("cpu0.yaml")
)
) )
) )
) cpu.rework {
for (plugin <- cpu.config.plugins) plugin match {
case plugin: DebugPlugin => plugin.debugClockDomain {
val fixedMtvec = new Rtl { plugin.io.bus.setAsDirectionLess()
override def getName(): String = "Fixed MTVEC" val jtag = slave(new Jtag())
override def getRtlPath(): String = "fixedMtvec.v" .setName("jtag")
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l))).setDefinitionName(getRtlPath().split("\\.").head)) jtag <> plugin.io.bus.fromJtag()
} }
case _ =>
val writeOnlyMtvec = new Rtl { }
override def getName(): String = "write only MTVEC" }
override def getRtlPath(): String = "woMtvec.v" cpu
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = WRITE_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
}
val readWriteMtvec = new Rtl {
override def getName(): String = "read write MTVEC"
override def getRtlPath(): String = "wrMtvec.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE))).setDefinitionName(getRtlPath().split("\\.").head))
}
val fixedMtvecRoCounter = new Rtl {
override def getName(): String = "Fixed MTVEC, read only mcycle/minstret"
override def getRtlPath(): String = "fixedMtvecRoCounter.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
} }
val rwMtvecRoCounter = new Rtl { val vexDebug = new Rtl {
override def getName(): String = "read write MTVEC, read only mcycle/minstret" override def getName(): String = "vexDebug"
override def getRtlPath(): String = "readWriteMtvecRoCounter.v" override def getRtlPath(): String = "vexDebug.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE, mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head)) SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l)),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset")))
).setDefinitionName(getRtlPath().split("\\.").head))
} }
// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp) // val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
val rtls = List(fixedMtvec, writeOnlyMtvec, readWriteMtvec,fixedMtvecRoCounter, rwMtvecRoCounter) val rtls = List(vexDebug)
// val rtls = List(smallest) // val rtls = List(smallest)
val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1)