Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

fix too early

Browse source 
# Conflicts:
#	src/main/scala/vexriscv/demo/SynthesisBench.scala
This commit is contained in:
Dolu1990 2023-02-19 09:51:18 +01:00
parent 1c38b6ec66
commit bbbfc7ee6b
1 changed files with 66 additions and 74 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

138
src/main/scala/vexriscv/demo/SynthesisBench.scala
View file

@ -409,88 +409,80 @@ object VexRiscvCustomSynthesisBench {
def main(args: Array[String]) {
def gen(csr : CsrPlugin) = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new IBusSimplePlugin(
resetVector = 0x80000000l,
cmdForkOnSecondStage = false,
cmdForkPersistence = false,
prediction = NONE,
catchAccessFault = false,
compressedGen = false
),
new DBusSimplePlugin(
catchAddressMisaligned = false,
catchAccessFault = false
),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false,
executeInsertion = true
),
csr,
new FullBarrelShifterPlugin(),
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false
),
new YamlPlugin("cpu0.yaml")
def gen(csr : CsrPlugin, p : Plugin[VexRiscv]) = {
val cpu = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
p,
new IBusSimplePlugin(
resetVector = 0x80000000l,
cmdForkOnSecondStage = false,
cmdForkPersistence = false,
prediction = NONE,
catchAccessFault = false,
compressedGen = false
),
new DBusSimplePlugin(
catchAddressMisaligned = false,
catchAccessFault = false
),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false,
executeInsertion = true
),
csr,
new FullBarrelShifterPlugin(),
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false
),
new YamlPlugin("cpu0.yaml")
)
)
)
)
val fixedMtvec = new Rtl {
override def getName(): String = "Fixed MTVEC"
override def getRtlPath(): String = "fixedMtvec.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l))).setDefinitionName(getRtlPath().split("\\.").head))
}
val writeOnlyMtvec = new Rtl {
override def getName(): String = "write only MTVEC"
override def getRtlPath(): String = "woMtvec.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = WRITE_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
}
val readWriteMtvec = new Rtl {
override def getName(): String = "read write MTVEC"
override def getRtlPath(): String = "wrMtvec.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE))).setDefinitionName(getRtlPath().split("\\.").head))
}
val fixedMtvecRoCounter = new Rtl {
override def getName(): String = "Fixed MTVEC, read only mcycle/minstret"
override def getRtlPath(): String = "fixedMtvecRoCounter.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l).copy(mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
cpu.rework {
for (plugin <- cpu.config.plugins) plugin match {
case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag())
.setName("jtag")
jtag <> plugin.io.bus.fromJtag()
}
case _ =>
}
}
cpu
}
val rwMtvecRoCounter = new Rtl {
override def getName(): String = "read write MTVEC, read only mcycle/minstret"
override def getRtlPath(): String = "readWriteMtvecRoCounter.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(null).copy(mtvecAccess = READ_WRITE, mcycleAccess = READ_ONLY, minstretAccess = READ_ONLY))).setDefinitionName(getRtlPath().split("\\.").head))
val vexDebug = new Rtl {
override def getName(): String = "vexDebug"
override def getRtlPath(): String = "vexDebug.v"
SpinalVerilog(gen(new CsrPlugin(CsrPluginConfig.smallest(0x80000000l)),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset")))
).setDefinitionName(getRtlPath().split("\\.").head))
}
// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
val rtls = List(fixedMtvec, writeOnlyMtvec, readWriteMtvec,fixedMtvecRoCounter, rwMtvecRoCounter)
val rtls = List(vexDebug)
// val rtls = List(smallest)
val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1)