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Fix SmpCluster jtag

This commit is contained in:
Dolu1990 2020-05-27 14:19:37 +02:00
parent 18cce053a3
commit bc4a2c3747
3 changed files with 10 additions and 13 deletions
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17
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -51,12 +51,12 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
} }
case _ => case _ =>
} }
if(cpuId == 0) cpuConfig.plugins += new DebugPlugin(debugClockDomain)
val core = new VexRiscv(cpuConfig) val core = new VexRiscv(cpuConfig)
core.plugins.foreach { core.plugins.foreach {
case plugin: IBusCachedPlugin => iBus = plugin.iBus.toBmb() case plugin: IBusCachedPlugin => iBus = plugin.iBus.toBmb()
case plugin: DBusCachedPlugin => dBus = plugin.dBus.toBmb().pipelined(cmdValid = true) case plugin: DBusCachedPlugin => dBus = plugin.dBus.toBmb().pipelined(cmdValid = true)
case plugin: CsrPlugin => { case plugin: CsrPlugin => {
plugin.externalMhartId := cpuId
plugin.softwareInterrupt := io.softwareInterrupts(cpuId) plugin.softwareInterrupt := io.softwareInterrupts(cpuId)
plugin.externalInterrupt := io.externalInterrupts(cpuId) plugin.externalInterrupt := io.externalInterrupts(cpuId)
plugin.timerInterrupt := io.timerInterrupts(cpuId) plugin.timerInterrupt := io.timerInterrupts(cpuId)
@ -113,12 +113,12 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
object VexRiscvSmpClusterGen { object VexRiscvSmpClusterGen {
def vexRiscvConfig(hartIdWidth : Int, def vexRiscvConfig(hartId : Int,
hartId : Int,
ioRange : UInt => Bool = (x => x(31 downto 28) === 0xF), ioRange : UInt => Bool = (x => x(31 downto 28) === 0xF),
resetVector : Long = 0x80000000l) = { resetVector : Long = 0x80000000l,
val iBusWidth = 128 iBusWidth : Int = 128,
val dBusWidth = 64 dBusWidth : Int = 64) = {
val config = VexRiscvConfig( val config = VexRiscvConfig(
plugins = List( plugins = List(
new MmuPlugin( new MmuPlugin(
@ -213,7 +213,7 @@ object VexRiscvSmpClusterGen {
mulUnrollFactor = 32, mulUnrollFactor = 32,
divUnrollFactor = 1 divUnrollFactor = 1
), ),
new CsrPlugin(CsrPluginConfig.openSbi(misa = Riscv.misaToInt("imas")).copy(withExternalMhartid = true, mhartidWidth = hartIdWidth)), new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas"))),
new BranchPlugin( new BranchPlugin(
earlyBranch = false, earlyBranch = false,
catchAddressMisaligned = true, catchAddressMisaligned = true,
@ -222,14 +222,13 @@ object VexRiscvSmpClusterGen {
new YamlPlugin(s"cpu$hartId.yaml") new YamlPlugin(s"cpu$hartId.yaml")
) )
) )
if(hartId == 0) config.plugins += new DebugPlugin(null)
config config
} }
def vexRiscvCluster(cpuCount : Int, resetVector : Long = 0x80000000l) = VexRiscvSmpCluster( def vexRiscvCluster(cpuCount : Int, resetVector : Long = 0x80000000l) = VexRiscvSmpCluster(
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")), debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
p = VexRiscvSmpClusterParameter( p = VexRiscvSmpClusterParameter(
cpuConfigs = List.tabulate(cpuCount) { cpuConfigs = List.tabulate(cpuCount) {
vexRiscvConfig(log2Up(cpuCount), _, resetVector = resetVector) vexRiscvConfig(_, resetVector = resetVector)
} }
) )
) )

2
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
View File

@ -342,7 +342,6 @@ object VexRiscvLitexSmpClusterGen extends App {
cluster = VexRiscvSmpClusterParameter( cluster = VexRiscvSmpClusterParameter(
cpuConfigs = List.tabulate(cpuCount) { hartId => cpuConfigs = List.tabulate(cpuCount) { hartId =>
vexRiscvConfig( vexRiscvConfig(
hartIdWidth = log2Up(cpuCount),
hartId = hartId, hartId = hartId,
ioRange = address => address.msb, ioRange = address => address.msb,
resetVector = 0 resetVector = 0
@ -382,7 +381,6 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
cluster = VexRiscvSmpClusterParameter( cluster = VexRiscvSmpClusterParameter(
cpuConfigs = List.tabulate(cpuCount) { hartId => cpuConfigs = List.tabulate(cpuCount) { hartId =>
vexRiscvConfig( vexRiscvConfig(
hartIdWidth = log2Up(cpuCount),
hartId = hartId, hartId = hartId,
ioRange = address => address(31 downto 28) === 0xF, ioRange = address => address(31 downto 28) === 0xF,
resetVector = 0x80000000l resetVector = 0x80000000l

4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -87,12 +87,12 @@ object CsrPluginConfig{
def small : CsrPluginConfig = small(0x00000020l) def small : CsrPluginConfig = small(0x00000020l)
def smallest : CsrPluginConfig = smallest(0x00000020l) def smallest : CsrPluginConfig = smallest(0x00000020l)
def openSbi(misa : Int) = CsrPluginConfig( def openSbi(mhartid : Int, misa : Int) = CsrPluginConfig(
catchIllegalAccess = true, catchIllegalAccess = true,
mvendorid = 0, mvendorid = 0,
marchid = 0, marchid = 0,
mimpid = 0, mimpid = 0,
mhartid = 0, mhartid = mhartid,
misaExtensionsInit = misa, misaExtensionsInit = misa,
misaAccess = CsrAccess.READ_ONLY, misaAccess = CsrAccess.READ_ONLY,
mtvecAccess = CsrAccess.READ_WRITE, //Could have been WRITE_ONLY :( mtvecAccess = CsrAccess.READ_WRITE, //Could have been WRITE_ONLY :(