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Add vexRiscvConfig.withMmu option

This commit is contained in:
Dolu1990 2021-01-21 13:28:04 +01:00
parent 04499c0b76
commit bcd140fc42
1 changed files with 8 additions and 3 deletions
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11
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -15,7 +15,7 @@ import spinal.lib.generator.Handle
import spinal.lib.misc.plic.PlicMapping import spinal.lib.misc.plic.PlicMapping
import spinal.lib.system.debugger.SystemDebuggerConfig import spinal.lib.system.debugger.SystemDebuggerConfig
import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig} import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin} import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin} import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin}
import scala.collection.mutable import scala.collection.mutable
@ -160,12 +160,17 @@ object VexRiscvSmpClusterGen {
dCacheWays : Int = 2, dCacheWays : Int = 2,
iBusRelax : Boolean = false, iBusRelax : Boolean = false,
earlyBranch : Boolean = false, earlyBranch : Boolean = false,
dBusCmdMasterPipe : Boolean = false) = { dBusCmdMasterPipe : Boolean = false,
withMmu : Boolean = true,
withSupervisor : Boolean = true
) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
val config = VexRiscvConfig( val config = VexRiscvConfig(
plugins = List( plugins = List(
new MmuPlugin( if(withMmu)new MmuPlugin(
ioRange = ioRange
)else new StaticMemoryTranslatorPlugin(
ioRange = ioRange ioRange = ioRange
), ),
//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config //Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config