Add vexRiscvConfig.withMmu option
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@ -15,7 +15,7 @@ import spinal.lib.generator.Handle
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import spinal.lib.misc.plic.PlicMapping
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import spinal.lib.system.debugger.SystemDebuggerConfig
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, StaticMemoryTranslatorPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvBmbGenerator, VexRiscvConfig, plugin}
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import scala.collection.mutable
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@ -160,12 +160,17 @@ object VexRiscvSmpClusterGen {
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dCacheWays : Int = 2,
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iBusRelax : Boolean = false,
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earlyBranch : Boolean = false,
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dBusCmdMasterPipe : Boolean = false) = {
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dBusCmdMasterPipe : Boolean = false,
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withMmu : Boolean = true,
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withSupervisor : Boolean = true
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) = {
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assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
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assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
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val config = VexRiscvConfig(
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plugins = List(
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new MmuPlugin(
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if(withMmu)new MmuPlugin(
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ioRange = ioRange
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)else new StaticMemoryTranslatorPlugin(
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ioRange = ioRange
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),
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//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
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