Expand SATP register to 22 bits per spec

Vex only implements a 32-bit PA which does not take advantage
of the potetnial 32-bit space in Sv32 mode. Very reasonably,
Vex simply discards the top two unused bits.

However, the spec does require that the register occupy all 22
bits and it is possible for the OS to use the extra bits up top
for some bookkeeping purpose. This commit proposes to expand the
register to occupy the full 22 bits in case an OS is written
to utilize the full width of the register as written in the spec.

src/main/scala/vexriscv/plugin/MmuPlugin.scala

@@ -94,7 +94,8 @@ class MmuPlugin(ioRange : UInt => Bool,
       val satp = new Area {
         val mode = RegInit(False)
         val asid = Reg(Bits(9 bits))
-        val ppn = Reg(UInt(20 bits))
+        // Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use.
+        val ppn = Reg(UInt(22 bits))
       }
 
       for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv)
@@ -233,7 +234,8 @@ class MmuPlugin(ioRange : UInt => Bool,
           }
           is(State.L1_CMD){
             dBusAccess.cmd.valid := True
-            dBusAccess.cmd.address := csr.satp.ppn @@ vpn(1) @@ U"00"
+            // RV spec allows for 34-bit phys address in Sv32 mode; we only implement 32 bits and ignore the top 2 bits of satp.
+            dBusAccess.cmd.address := csr.satp.ppn(19 downto 0) @@ vpn(1) @@ U"00"
             when(dBusAccess.cmd.ready){
               state := State.L1_RSP
             }