PcManager now drive PC asyncronously (use 1 cycle less in jump)
Fix bypass logic when read/write r0 Disable REGFILE_WRITE_VALID in decod stage when r0 is written
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83232e9860
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bf5bebda08
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@ -361,7 +361,7 @@ class NoPredictionBranchPlugin(earlyBranch : Boolean) extends Plugin[VexRiscv]{
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jumpInterface.payload := input(BRANCH_CALC)
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when(jumpInterface.valid) {
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prefetch.arbitration.removeIt := True
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//prefetch.arbitration.removeIt := True
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fetch.arbitration.removeIt := True
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decode.arbitration.removeIt := True
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if(!earlyBranch) execute.arbitration.removeIt := True
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@ -376,7 +376,7 @@ trait PcManagerService{
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def createJumpInterface(stage : Stage) : Flow[UInt]
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}
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class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boolean) extends Plugin[VexRiscv] with PcManagerService{
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class PcManagerSimplePlugin(resetVector : BigInt,fastPcCalculation : Boolean) extends Plugin[VexRiscv] with PcManagerService{
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//FetchService interface
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@ -400,12 +400,17 @@ class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boo
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//PC calculation without Jump
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val pc = Reg(UInt(pcWidth bits)) init(resetVector) addAttribute("verilator public")
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when(arbitration.isFiring){
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val pcPlus4 = pc + 4
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if(fastFetchCmdPcCalculation) pcPlus4.addAttribute("keep") //Disallow to use the carry in as enable
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pc := pcPlus4
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val inc = RegInit(False)
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val pcNext = if(fastPcCalculation){
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val pcPlus4 = pc + U(4)
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pcPlus4.addAttribute("keep")
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Mux(inc,pcPlus4,pc)
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}else{
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pc + Mux(inc,U(4),U(0))
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}
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val samplePcNext = False
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//FetchService hardware implementation
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val jump = if(jumpInfos.length != 0) new Area {
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val sortedByStage = jumpInfos.sortWith((a, b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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@ -418,12 +423,21 @@ class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boo
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//Register managments
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when(pcLoad.valid) {
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pc := pcLoad.payload
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inc := False
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samplePcNext := True
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pcNext := pcLoad.payload
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}
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}
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when(arbitration.isFiring){
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inc := True
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samplePcNext := True
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}
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when(samplePcNext) { pc := pcNext }
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//Pipeline insertions
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insert(PC) := pc
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insert(PC) := pcNext
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}
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}
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}
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@ -589,6 +603,11 @@ class HazardSimplePlugin(bypassExecute : Boolean,bypassMemory: Boolean,bypassWri
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val src0Hazard = False
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val src1Hazard = False
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//Disable rd0 write in decoding stage
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when(decode.input(INSTRUCTION)(rdRange) === 0) {
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decode.input(REGFILE_WRITE_VALID) := False
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}
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def trackHazardWithStage(stage : Stage,bypassable : Boolean, runtimeBypassable : Stageable[Bool]): Unit ={
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val runtimeBypassableValue = if(runtimeBypassable != null) stage.input(runtimeBypassable) else True
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val addr0Match = stage.input(INSTRUCTION)(rdRange) === decode.input(INSTRUCTION)(rs1Range)
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@ -630,10 +649,10 @@ class HazardSimplePlugin(bypassExecute : Boolean,bypassMemory: Boolean,bypassWri
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when(writeBackBuffer.valid) {
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if (bypassWriteBackBuffer) {
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when(addr0Match) {
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decode.input(REG1) := writeBackWrites.data
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decode.input(REG1) := writeBackBuffer.data
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}
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when(addr1Match) {
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decode.input(REG2) := writeBackWrites.data
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decode.input(REG2) := writeBackBuffer.data
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}
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} else {
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when(addr0Match) {
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@ -657,7 +676,7 @@ class HazardSimplePlugin(bypassExecute : Boolean,bypassMemory: Boolean,bypassWri
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src1Hazard := False
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}
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when(src0Hazard || src1Hazard){
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when(decode.arbitration.isValid && (src0Hazard || src1Hazard)){
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decode.arbitration.haltIt := True
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}
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}
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@ -939,7 +958,7 @@ object TopLevel {
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)
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config.plugins ++= List(
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new PcManagerSimplePlugin(0, false),
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new PcManagerSimplePlugin(0, true),
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new IBusSimplePlugin(true),
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new DecoderSimplePlugin,
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new RegFilePlugin(SYNC),
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@ -947,8 +966,8 @@ object TopLevel {
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new SrcPlugin,
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new FullBarrielShifterPlugin,
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new DBusSimplePlugin,
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// new HazardSimplePlugin(true,true,true,true),
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new HazardSimplePlugin(false, false, false, false),
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new HazardSimplePlugin(true,true,true,true),
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// new HazardSimplePlugin(false, false, false, false),
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new NoPredictionBranchPlugin(false)
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)
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@ -0,0 +1,118 @@
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build/testA.elf: file format elf32-littleriscv
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Disassembly of section .yolo:
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00000000 <testA2WithNop-0x17c>:
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0: 00000013 nop
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4: 00000013 nop
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8: 00000013 nop
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c: 00000013 nop
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10: 00000013 nop
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14: 00000013 nop
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18: 00000013 nop
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1c: 00a00093 li ra,10
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20: 00000013 nop
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24: 00000013 nop
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28: 00000013 nop
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2c: 00000013 nop
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30: 00000013 nop
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34: 00000013 nop
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38: 00000013 nop
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3c: 01400113 li sp,20
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40: 00000013 nop
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44: 00000013 nop
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48: 00000013 nop
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4c: 00000013 nop
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50: 00000013 nop
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54: 00000013 nop
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58: 00000013 nop
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5c: 01e08193 addi gp,ra,30
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60: 00000013 nop
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64: 00000013 nop
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68: 00000013 nop
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6c: 00000013 nop
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70: 00000013 nop
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74: 00000013 nop
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78: 00000013 nop
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7c: 00218233 add tp,gp,sp
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80: 00000013 nop
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84: 00000013 nop
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88: 00000013 nop
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8c: 00000013 nop
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90: 00000013 nop
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94: 00000013 nop
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98: 00000013 nop
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9c: 00a00093 li ra,10
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a0: 01400113 li sp,20
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a4: 01e08193 addi gp,ra,30
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a8: 00218233 add tp,gp,sp
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ac: 00000013 nop
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b0: 00000013 nop
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b4: 00000013 nop
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b8: 00000013 nop
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bc: 00000013 nop
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c0: 00000013 nop
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c4: 00000013 nop
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c8: 00000013 nop
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cc: 00000013 nop
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d0: 00000013 nop
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d4: 00000013 nop
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d8: 00000013 nop
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dc: 00000013 nop
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e0: 00000013 nop
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e4: 00000013 nop
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e8: 00000013 nop
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ec: 00000013 nop
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f0: 00000013 nop
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f4: 00000013 nop
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f8: 00000013 nop
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fc: 00000013 nop
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100: 00000013 nop
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104: 00000013 nop
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108: 00000013 nop
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10c: 00000013 nop
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110: 00000013 nop
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114: 00000013 nop
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118: 00000013 nop
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11c: 00100293 li t0,1
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120: 00000013 nop
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124: 00000013 nop
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128: 00000013 nop
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12c: 00000013 nop
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130: 00000013 nop
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134: 00000013 nop
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138: 00000013 nop
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13c: 0400006f j 17c <testA2WithNop>
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140: 00000013 nop
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144: 00000013 nop
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148: 00000013 nop
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14c: 00000013 nop
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150: 00000013 nop
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154: 00000013 nop
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158: 00000013 nop
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15c: 00200313 li t1,2
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160: 00000013 nop
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164: 00000013 nop
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168: 00000013 nop
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16c: 00000013 nop
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170: 00000013 nop
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174: 00000013 nop
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178: 00000013 nop
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0000017c <testA2WithNop>:
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17c: 00300393 li t2,3
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180: 00000013 nop
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184: 00000013 nop
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188: 00000013 nop
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18c: 00000013 nop
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190: 00000013 nop
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194: 00000013 nop
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198: 00000013 nop
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19c: 00100293 li t0,1
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1a0: 0080006f j 1a8 <testA2WithoutNop>
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1a4: 00200313 li t1,2
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000001a8 <testA2WithoutNop>:
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1a8: 00300393 li t2,3
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