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VexRiscv
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PcManager now drive PC asyncronously (use 1 cycle less in jump) 

Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
This commit is contained in:
Charles Papon 2017-03-15 21:10:44 +01:00
parent 83232e9860
commit bf5bebda08
2 changed files with 151 additions and 14 deletions
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47
src/main/scala/SpinalRiscv/TopLevel.scala
View File

@ -361,7 +361,7 @@ class NoPredictionBranchPlugin(earlyBranch : Boolean) extends Plugin[VexRiscv]{
jumpInterface.payload := input(BRANCH_CALC)
when(jumpInterface.valid) {
prefetch.arbitration.removeIt := True
//prefetch.arbitration.removeIt := True
fetch.arbitration.removeIt := True
decode.arbitration.removeIt := True
if(!earlyBranch) execute.arbitration.removeIt := True
@ -376,7 +376,7 @@ trait PcManagerService{
def createJumpInterface(stage : Stage) : Flow[UInt]
}
class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boolean) extends Plugin[VexRiscv] with PcManagerService{
class PcManagerSimplePlugin(resetVector : BigInt,fastPcCalculation : Boolean) extends Plugin[VexRiscv] with PcManagerService{
//FetchService interface
@ -400,12 +400,17 @@ class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boo
//PC calculation without Jump
val pc = Reg(UInt(pcWidth bits)) init(resetVector) addAttribute("verilator public")
when(arbitration.isFiring){
val pcPlus4 = pc + 4
if(fastFetchCmdPcCalculation) pcPlus4.addAttribute("keep") //Disallow to use the carry in as enable
pc := pcPlus4
val inc = RegInit(False)
val pcNext = if(fastPcCalculation){
val pcPlus4 = pc + U(4)
pcPlus4.addAttribute("keep")
Mux(inc,pcPlus4,pc)
}else{
pc + Mux(inc,U(4),U(0))
}
val samplePcNext = False
//FetchService hardware implementation
val jump = if(jumpInfos.length != 0) new Area {
val sortedByStage = jumpInfos.sortWith((a, b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
@ -418,12 +423,21 @@ class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boo
//Register managments
when(pcLoad.valid) {
pc := pcLoad.payload
inc := False
samplePcNext := True
pcNext := pcLoad.payload
}
}
when(arbitration.isFiring){
inc := True
samplePcNext := True
}
when(samplePcNext) { pc := pcNext }
//Pipeline insertions
insert(PC) := pc
insert(PC) := pcNext
}
}
}
@ -589,6 +603,11 @@ class HazardSimplePlugin(bypassExecute : Boolean,bypassMemory: Boolean,bypassWri
val src0Hazard = False
val src1Hazard = False
//Disable rd0 write in decoding stage
when(decode.input(INSTRUCTION)(rdRange) === 0) {
decode.input(REGFILE_WRITE_VALID) := False
}
def trackHazardWithStage(stage : Stage,bypassable : Boolean, runtimeBypassable : Stageable[Bool]): Unit ={
val runtimeBypassableValue = if(runtimeBypassable != null) stage.input(runtimeBypassable) else True
val addr0Match = stage.input(INSTRUCTION)(rdRange) === decode.input(INSTRUCTION)(rs1Range)
@ -630,10 +649,10 @@ class HazardSimplePlugin(bypassExecute : Boolean,bypassMemory: Boolean,bypassWri
when(writeBackBuffer.valid) {
if (bypassWriteBackBuffer) {
when(addr0Match) {
decode.input(REG1) := writeBackWrites.data
decode.input(REG1) := writeBackBuffer.data
}
when(addr1Match) {
decode.input(REG2) := writeBackWrites.data
decode.input(REG2) := writeBackBuffer.data
}
} else {
when(addr0Match) {
@ -657,7 +676,7 @@ class HazardSimplePlugin(bypassExecute : Boolean,bypassMemory: Boolean,bypassWri
src1Hazard := False
}
when(src0Hazard || src1Hazard){
when(decode.arbitration.isValid && (src0Hazard || src1Hazard)){
decode.arbitration.haltIt := True
}
}
@ -939,7 +958,7 @@ object TopLevel {
)
config.plugins ++= List(
new PcManagerSimplePlugin(0, false),
new PcManagerSimplePlugin(0, true),
new IBusSimplePlugin(true),
new DecoderSimplePlugin,
new RegFilePlugin(SYNC),
@ -947,8 +966,8 @@ object TopLevel {
new SrcPlugin,
new FullBarrielShifterPlugin,
new DBusSimplePlugin,
// new HazardSimplePlugin(true,true,true,true),
new HazardSimplePlugin(false, false, false, false),
new HazardSimplePlugin(true,true,true,true),
// new HazardSimplePlugin(false, false, false, false),
new NoPredictionBranchPlugin(false)
)

118
src/test/resources/asm/testA.asm Normal file
View File

@ -0,0 +1,118 @@
build/testA.elf: file format elf32-littleriscv
Disassembly of section .yolo:
00000000 <testA2WithNop-0x17c>:
0: 00000013 nop
4: 00000013 nop
8: 00000013 nop
c: 00000013 nop
10: 00000013 nop
14: 00000013 nop
18: 00000013 nop
1c: 00a00093 li ra,10
20: 00000013 nop
24: 00000013 nop
28: 00000013 nop
2c: 00000013 nop
30: 00000013 nop
34: 00000013 nop
38: 00000013 nop
3c: 01400113 li sp,20
40: 00000013 nop
44: 00000013 nop
48: 00000013 nop
4c: 00000013 nop
50: 00000013 nop
54: 00000013 nop
58: 00000013 nop
5c: 01e08193 addi gp,ra,30
60: 00000013 nop
64: 00000013 nop
68: 00000013 nop
6c: 00000013 nop
70: 00000013 nop
74: 00000013 nop
78: 00000013 nop
7c: 00218233 add tp,gp,sp
80: 00000013 nop
84: 00000013 nop
88: 00000013 nop
8c: 00000013 nop
90: 00000013 nop
94: 00000013 nop
98: 00000013 nop
9c: 00a00093 li ra,10
a0: 01400113 li sp,20
a4: 01e08193 addi gp,ra,30
a8: 00218233 add tp,gp,sp
ac: 00000013 nop
b0: 00000013 nop
b4: 00000013 nop
b8: 00000013 nop
bc: 00000013 nop
c0: 00000013 nop
c4: 00000013 nop
c8: 00000013 nop
cc: 00000013 nop
d0: 00000013 nop
d4: 00000013 nop
d8: 00000013 nop
dc: 00000013 nop
e0: 00000013 nop
e4: 00000013 nop
e8: 00000013 nop
ec: 00000013 nop
f0: 00000013 nop
f4: 00000013 nop
f8: 00000013 nop
fc: 00000013 nop
100: 00000013 nop
104: 00000013 nop
108: 00000013 nop
10c: 00000013 nop
110: 00000013 nop
114: 00000013 nop
118: 00000013 nop
11c: 00100293 li t0,1
120: 00000013 nop
124: 00000013 nop
128: 00000013 nop
12c: 00000013 nop
130: 00000013 nop
134: 00000013 nop
138: 00000013 nop
13c: 0400006f j 17c <testA2WithNop>
140: 00000013 nop
144: 00000013 nop
148: 00000013 nop
14c: 00000013 nop
150: 00000013 nop
154: 00000013 nop
158: 00000013 nop
15c: 00200313 li t1,2
160: 00000013 nop
164: 00000013 nop
168: 00000013 nop
16c: 00000013 nop
170: 00000013 nop
174: 00000013 nop
178: 00000013 nop
0000017c <testA2WithNop>:
17c: 00300393 li t2,3
180: 00000013 nop
184: 00000013 nop
188: 00000013 nop
18c: 00000013 nop
190: 00000013 nop
194: 00000013 nop
198: 00000013 nop
19c: 00100293 li t0,1
1a0: 0080006f j 1a8 <testA2WithoutNop>
1a4: 00200313 li t1,2
000001a8 <testA2WithoutNop>:
1a8: 00300393 li t2,3