Smp spec update, add Interface subsets (writeOnly, readOnly)
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@ -57,6 +57,11 @@ One full coherent interface is composed of 3 inner interfaces, them-self compose
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- read (M -> readCmd- > S -> readRsp -> M -> readAck -> S)
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- probe (S -> probeCmd -> M -> probeRsp -> S)
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The following streams could physically be merges in order to reduce the number of arbitration :
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- writeCmd, probeRsp, readAck
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- writeRsp, readRsp
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### Read interface
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Used by masters to obtain new memory copies and make copies unique (used to write them).
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@ -67,7 +72,7 @@ Composed of 3 stream :
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|---------|-----------|----------|
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| readCmd | M -> S | Emit memory read and cache management commands |
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| readRsp | M <- S | Return some data and/or a status from readCmd |
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| readAck | M -> S | Return ACK from readRsp to syncronize the interconnect status |
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| readAck | M -> S | Return ACK from readRsp to synchronize the interconnect status |
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### Write interface
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@ -192,3 +197,20 @@ In other words :
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Masters can emit writeCmd and wait their writeRsp completion before answering probes commands.
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Slaves can emit probeCmd and wait their proveRsp completion before answering reads.
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Slaves can emit readRsp and wait on their readAck completion before doing anything else
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## Interface subsets
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There is a few cases where you could need a specific subset of the coherent interface :
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- Instruction caches do not necessarily need to maintain the coherency with the memory system.
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- DMA need to read and write the memory system, but are cache-less (no probe)
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### ReadOnly interface without maintained coherency
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Such interface is only composed of the read bus on which the readCmd stream can only use readOnce requests
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### WriteOnly interface
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In such interface, there is no read/probe buses, but only a writeCmd and a writeRsp stream. The writeCmd will invalidate other memory copies, then write into the memory while the writeRsp will return a writeSuccess/writeError status.
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