Refractoring of some arbitration signals
Add UART into Murax
This commit is contained in:
parent
8708d2482f
commit
c16a53c388
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@ -5,6 +5,8 @@ set_io io_H16 H16
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set_io io_G15 G15
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set_io io_G16 G16
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set_io io_F15 F15
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set_io io_B12 B12
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set_io io_B10 B10
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set_io io_led[0] B5
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set_io io_led[1] B4
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set_io io_led[2] A2
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@ -6,6 +6,8 @@ module toplevel(
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input io_G15,
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output io_G16,
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input io_F15,
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output io_B12,
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input io_B10,
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output [7:0] io_led
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);
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@ -36,6 +38,8 @@ module toplevel(
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.io_jtag_tms(io_F15),
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.io_gpioA_read (io_gpioA_read),
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.io_gpioA_write (io_gpioA_write),
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.io_gpioA_writeEnable(io_gpioA_writeEnable)
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.io_gpioA_writeEnable(io_gpioA_writeEnable),
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.io_uart_txd(io_B12),
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.io_uart_rxd(io_B10)
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);
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endmodule
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@ -117,8 +117,8 @@ trait Pipeline {
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}
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for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
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stage.arbitration.isStuckByOthers := stage.arbitration.haltItByOther || stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltIt/* && !s.arbitration.removeIt*/).foldLeft(False)(_ || _)
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stage.arbitration.isStuck := stage.arbitration.haltIt || stage.arbitration.isStuckByOthers
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stage.arbitration.isStuckByOthers := stage.arbitration.haltByOther || stages.takeRight(stages.length - stageIndex - 1).map(s => s.arbitration.haltItself/* && !s.arbitration.removeIt*/).foldLeft(False)(_ || _)
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stage.arbitration.isStuck := stage.arbitration.haltItself || stage.arbitration.isStuckByOthers
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stage.arbitration.isFiring := stage.arbitration.isValid && !stage.arbitration.isStuck && !stage.arbitration.removeIt
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}
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@ -45,15 +45,16 @@ class Stage() extends Area{
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val arbitration = new Area{
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val haltIt = False
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val haltItByOther = False
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val removeIt = False
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val flushAll = False
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val isValid = RegInit(False)
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val isStuck = Bool
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val isFlushed = Bool
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val isStuckByOthers = Bool
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val isFiring = Bool
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val haltItself = False //user settable, stuck the instruction, should only be set by the instruction itself
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val haltByOther = False //When settable, stuck the instruction, should only be set by something else than the stucked instruction
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val removeIt = False //When settable, unschedule the instruction as if it was never executed (no side effect)
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val flushAll = False //When settable, unschedule instructions in the current stage and all prior ones
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val isValid = RegInit(False) //Inform if a instruction is in the current stage
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val isStuck = Bool //Inform if the instruction is stuck (haltItself || haltByOther)
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val isStuckByOthers = Bool //Inform if the instruction is stuck by sombody else
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def isRemoved = removeIt //Inform if the instruction is going to be unschedule the current cycle
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val isFlushed = Bool //Inform if the instruction is flushed (flushAll set in the current or subsequents stages)
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val isFiring = Bool //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt)
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}
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@ -33,63 +33,63 @@ object TestsWorkspace {
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plugins = List(
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new PcManagerSimplePlugin(
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resetVector = 0x00000000l,
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relaxedPcCalculation = true
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relaxedPcCalculation = false
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),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = true
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),
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine =32,
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// wayCount = 1,
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// wrappedMemAccess = true,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = true,
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// catchAccessFault = true,
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// catchMemoryTranslationMiss = true,
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// asyncTagMemory = false,
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// twoStageLogic = true
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// ),
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = true
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// ),
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new DBusSimplePlugin(
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catchAddressMisaligned = true,
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catchAccessFault = true,
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earlyInjection = false
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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),
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 4
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)
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),
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// new DBusCachedPlugin(
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// config = new DataCacheConfig(
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// cacheSize = 4096,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessError = true,
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// catchIllegal = true,
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// catchUnaligned = true,
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// catchMemoryTranslationMiss = true
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// ),
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//// memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 6
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// )
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = true,
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// earlyInjection = false
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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// memoryTranslatorPortConfig = null
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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),
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// new StaticMemoryTranslatorPlugin(
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// ioRange = _(31 downto 28) === 0xF
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// ),
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// new MemoryTranslatorPlugin(
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// tlbSize = 32,
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// virtualRange = _(31 downto 28) === 0xC,
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// ioRange = _(31 downto 28) === 0xF
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// ),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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@ -57,7 +57,7 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
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decode.input(config.INSTRUCTION).addAttribute(Verilator.public)
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decode.input(config.PC).addAttribute(Verilator.public)
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decode.arbitration.isValid.addAttribute(Verilator.public)
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decode.arbitration.haltIt.addAttribute(Verilator.public)
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decode.arbitration.haltItself.addAttribute(Verilator.public)
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writeBack.input(config.INSTRUCTION) keep() addAttribute(Verilator.public)
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writeBack.input(config.PC) keep() addAttribute(Verilator.public)
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writeBack.arbitration.isValid keep() addAttribute(Verilator.public)
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@ -5,7 +5,7 @@ import spinal.lib._
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import spinal.lib.bus.amba3.apb.{Apb3SlaveFactory, Apb3Decoder, Apb3Gpio, Apb3}
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.uart.Uart
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import spinal.lib.com.uart._
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import spinal.lib.io.TriStateArray
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import spinal.lib.misc.{InterruptCtrl, Timer, Prescaler}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrlExternal, PinsecTimerCtrl}
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@ -24,6 +24,7 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
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* - APB bus for peripherals
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* - 32 GPIO pin
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* - one 16 bits prescaler, two 16 bits timers
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* - one UART with tx/rx fifo
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*/
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@ -88,7 +89,7 @@ case class Murax(config : MuraxConfig) extends Component{
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//Peripherals IO
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val gpioA = master(TriStateArray(32 bits))
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// val uart = master(Uart())
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val uart = master(Uart())
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}
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@ -345,6 +346,28 @@ case class Murax(config : MuraxConfig) extends Component{
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)
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io.gpioA <> gpioACtrl.io.gpio
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val uartCtrlConfig = UartCtrlMemoryMappedConfig(
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uartCtrlConfig = UartCtrlGenerics(
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dataWidthMax = 8,
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clockDividerWidth = 20,
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preSamplingSize = 1,
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samplingSize = 3,
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postSamplingSize = 1
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),
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initConfig = UartCtrlInitConfig(
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baudrate = 115200,
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dataLength = 7, //7 => 8 bits
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parity = UartParityType.NONE,
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stop = UartStopType.ONE
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),
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busCanWriteClockDividerConfig = false,
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busCanWriteFrameConfig = false,
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txFifoDepth = 16,
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rxFifoDepth = 16
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)
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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uartCtrl.io.uart <> io.uart
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val timer = new Area{
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val apb = Apb3(
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addressWidth = 8,
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@ -380,6 +403,7 @@ case class Murax(config : MuraxConfig) extends Component{
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master = apbBridge.apb,
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slaves = List(
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gpioACtrl.io.apb -> (0x00000, 4 kB),
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uartCtrl.io.apb -> (0x10000, 4 kB),
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timer.apb -> (0x20000, 4 kB)
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)
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)
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@ -325,7 +325,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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//Used to make the pipeline empty softly (for interrupts)
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val pipelineLiberator = new Area{
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val enable = False
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prefetch.arbitration.haltItByOther setWhen(enable)
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prefetch.arbitration.haltByOther setWhen(enable)
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val done = ! List(fetch, decode, execute, memory).map(_.arbitration.isValid).orR
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}
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@ -413,7 +413,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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//Manage MRET instructions
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when(memory.input(ENV_CTRL) === EnvCtrlEnum.MRET) {
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memory.arbitration.haltIt := writeBack.arbitration.isValid
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memory.arbitration.haltItself := writeBack.arbitration.isValid
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when(memory.arbitration.isFiring) {
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jumpInterface.valid := True
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jumpInterface.payload := mepc
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@ -432,7 +432,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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//Manage WFI instructions
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if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){
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when(!interrupt){
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execute.arbitration.haltIt := True
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execute.arbitration.haltItself := True
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decode.arbitration.flushAll := True
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}
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}
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@ -461,7 +461,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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|| (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0)))
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val writeInstruction = arbitration.isValid && input(IS_CSR) && writeOpcode
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arbitration.haltIt setWhen(writeInstruction && !readDataRegValid)
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arbitration.haltItself setWhen(writeInstruction && !readDataRegValid)
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val writeEnable = writeInstruction && !arbitration.isStuckByOthers && !arbitration.removeIt && readDataRegValid
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when(arbitration.isValid && input(IS_CSR)) {
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@ -123,7 +123,7 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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cache.io.cpu.memory.isValid := arbitration.isValid && input(MEMORY_ENABLE)
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cache.io.cpu.memory.isStuck := arbitration.isStuck
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cache.io.cpu.memory.isRemoved := arbitration.removeIt
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arbitration.haltIt setWhen(cache.io.cpu.memory.haltIt)
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arbitration.haltItself setWhen(cache.io.cpu.memory.haltIt)
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cache.io.cpu.memory.mmuBus <> mmuBus
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}
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@ -148,7 +148,7 @@ class DBusCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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exceptionBus.code := 13
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}
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}
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arbitration.haltIt.setWhen(cache.io.cpu.writeBack.haltIt)
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arbitration.haltItself.setWhen(cache.io.cpu.writeBack.haltIt)
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val rspShifted = Bits(32 bits)
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rspShifted := cache.io.cpu.writeBack.data
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@ -210,7 +210,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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default -> input(RS2)(31 downto 0)
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)
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when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready && !input(ALIGNEMENT_FAULT)){
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arbitration.haltIt := True
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arbitration.haltItself := True
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}
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insert(MEMORY_ADDRESS_LOW) := dBus.cmd.address(1 downto 0)
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@ -222,7 +222,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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insert(MEMORY_READ_DATA) := dBus.rsp.data
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arbitration.haltIt setWhen(arbitration.isValid && input(MEMORY_ENABLE) && input(REGFILE_WRITE_VALID) && !dBus.rsp.ready)
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arbitration.haltItself setWhen(arbitration.isValid && input(MEMORY_ENABLE) && input(REGFILE_WRITE_VALID) && !dBus.rsp.ready)
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if(catchAccessFault || catchAddressMisaligned){
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if(!catchAccessFault){
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@ -161,7 +161,7 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] {
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when(io.bus.cmd.wr) {
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insertDecodeInstruction := True
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decode.arbitration.isValid setWhen (firstCycle)
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decode.arbitration.haltIt setWhen (secondCycle)
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decode.arbitration.haltItself setWhen (secondCycle)
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io.bus.cmd.ready := !(firstCycle || secondCycle || decode.arbitration.isValid)
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}
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}
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@ -180,14 +180,14 @@ class DebugPlugin(val debugClockDomain : ClockDomain) extends Plugin[VexRiscv] {
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when(execute.arbitration.isFiring && execute.input(IS_EBREAK)) {
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prefetch.arbitration.haltItByOther := True
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prefetch.arbitration.haltByOther := True
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decode.arbitration.flushAll := True
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haltIt := True
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haltedByBreak := True
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}
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when(haltIt) {
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prefetch.arbitration.haltItByOther := True
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prefetch.arbitration.haltByOther := True
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}
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when(stepIt && prefetch.arbitration.isFiring) {
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@ -47,7 +47,7 @@ class DivPlugin extends Plugin[VexRiscv]{
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when(arbitration.isValid && input(IS_DIV)) {
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divider.io.cmd.valid := !arbitration.isStuckByOthers && !arbitration.removeIt
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arbitration.haltIt := memory.arbitration.isValid && memory.input(IS_DIV)
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arbitration.haltItself := memory.arbitration.isValid && memory.input(IS_DIV)
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}
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}
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@ -59,7 +59,7 @@ class DivPlugin extends Plugin[VexRiscv]{
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divider.io.rsp.ready := !arbitration.isStuckByOthers
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when(arbitration.isValid && input(IS_DIV)) {
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arbitration.haltIt := !divider.io.rsp.valid
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arbitration.haltItself := !divider.io.rsp.valid
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input(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits
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}
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@ -12,6 +12,6 @@ class HazardPessimisticPlugin() extends Plugin[VexRiscv] {
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import pipeline.config._
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val writesInPipeline = List(execute,memory,writeBack).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(writeBack.arbitration.isValid && writeBack.input(REGFILE_WRITE_VALID))
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decode.arbitration.haltIt.setWhen(decode.arbitration.isValid && writesInPipeline.orR)
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decode.arbitration.haltItself.setWhen(decode.arbitration.isValid && writesInPipeline.orR)
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}
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}
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@ -92,7 +92,7 @@ class HazardSimplePlugin(bypassExecute : Boolean,
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}
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when(decode.arbitration.isValid && (src0Hazard || src1Hazard)){
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decode.arbitration.haltIt := True
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decode.arbitration.haltItself := True
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}
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}
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}
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@ -70,7 +70,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
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cache.io.cpu.prefetch.isValid := prefetch.arbitration.isValid
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cache.io.cpu.prefetch.isFiring := prefetch.arbitration.isFiring
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cache.io.cpu.prefetch.address := prefetch.output(PC)
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prefetch.arbitration.haltIt setWhen(cache.io.cpu.prefetch.haltIt)
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prefetch.arbitration.haltItself setWhen(cache.io.cpu.prefetch.haltIt)
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//Connect fetch cache side
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cache.io.cpu.fetch.isValid := fetch.arbitration.isValid
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@ -78,7 +78,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
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if(!twoStageLogic) cache.io.cpu.fetch.isStuckByOthers := fetch.arbitration.isStuckByOthers
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cache.io.cpu.fetch.address := fetch.output(PC)
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if(!twoStageLogic) {
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fetch.arbitration.haltIt setWhen (cache.io.cpu.fetch.haltIt)
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fetch.arbitration.haltItself setWhen (cache.io.cpu.fetch.haltIt)
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fetch.insert(INSTRUCTION) := cache.io.cpu.fetch.data
|
||||
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
|
||||
decode.insert(INSTRUCTION_READY) := True
|
||||
|
@ -100,7 +100,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
|
|||
|
||||
if(twoStageLogic){
|
||||
cache.io.cpu.decode.isValid := decode.arbitration.isValid && RegNextWhen(fetch.arbitration.isValid, !decode.arbitration.isStuck) //avoid inserted instruction from debug module
|
||||
decode.arbitration.haltIt.setWhen(cache.io.cpu.decode.haltIt)
|
||||
decode.arbitration.haltItself.setWhen(cache.io.cpu.decode.haltIt)
|
||||
cache.io.cpu.decode.isStuck := decode.arbitration.isStuck
|
||||
cache.io.cpu.decode.isUser := (if(privilegeService != null) privilegeService.isUser(writeBack) else False)
|
||||
cache.io.cpu.decode.address := decode.input(PC)
|
||||
|
@ -132,7 +132,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
|
|||
cache.io.flush.cmd.valid := True
|
||||
|
||||
when(!cache.io.flush.cmd.ready){
|
||||
arbitration.haltIt := True
|
||||
arbitration.haltItself := True
|
||||
} otherwise {
|
||||
decode.arbitration.flushAll := True
|
||||
}
|
||||
|
|
|
@ -117,7 +117,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
|
|||
//Emit iBus.cmd request
|
||||
iBus.cmd.valid := prefetch.arbitration.isValid && !prefetch.arbitration.removeIt && !prefetch.arbitration.isStuckByOthers && !(pendingCmd && !iBus.rsp.ready) //prefetch.arbitration.isValid && !prefetch.arbitration.isStuckByOthers
|
||||
iBus.cmd.pc := prefetch.output(PC)
|
||||
prefetch.arbitration.haltIt setWhen (!iBus.cmd.ready || (pendingCmd && !iBus.rsp.ready))
|
||||
prefetch.arbitration.haltItself setWhen (!iBus.cmd.ready || (pendingCmd && !iBus.rsp.ready))
|
||||
}
|
||||
|
||||
//Bus rsp buffer
|
||||
|
@ -144,9 +144,9 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
|
|||
fetch.insert(IBUS_ACCESS_ERROR) clearWhen(!fetch.arbitration.isValid) //Avoid interference with instruction injection from the debug plugin
|
||||
|
||||
if(interfaceKeepData)
|
||||
fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
|
||||
fetch.arbitration.haltItself setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
|
||||
else
|
||||
fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready && !rspBuffer.valid)
|
||||
fetch.arbitration.haltItself setWhen(fetch.arbitration.isValid && !iBus.rsp.ready && !rspBuffer.valid)
|
||||
|
||||
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
|
||||
decode.insert(INSTRUCTION_READY) := True
|
||||
|
|
|
@ -108,7 +108,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
|
|||
port.bus.rsp.allowWrite := cacheLine.allowWrite
|
||||
port.bus.rsp.allowExecute := cacheLine.allowExecute
|
||||
port.bus.rsp.allowUser := cacheLine.allowUser
|
||||
port.stage.arbitration.haltIt setWhen (port.bus.cmd.isValid && !cacheHit && !sharedMiss)
|
||||
port.stage.arbitration.haltItself setWhen (port.bus.cmd.isValid && !cacheHit && !sharedMiss)
|
||||
} otherwise {
|
||||
port.bus.rsp.physicalAddress := port.bus.cmd.virtualAddress
|
||||
port.bus.rsp.allowRead := True
|
||||
|
|
|
@ -168,7 +168,7 @@ class LightShifterPlugin extends Plugin[VexRiscv]{
|
|||
when(done){
|
||||
isActive := False
|
||||
} otherwise{
|
||||
arbitration.haltIt := True
|
||||
arbitration.haltItself := True
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -10,6 +10,6 @@ class SingleInstructionLimiterPlugin() extends Plugin[VexRiscv] {
|
|||
import pipeline._
|
||||
import pipeline.config._
|
||||
|
||||
prefetch.arbitration.haltItByOther.setWhen(List(fetch,decode,execute,memory,writeBack).map(_.arbitration.isValid).orR)
|
||||
prefetch.arbitration.haltByOther.setWhen(List(fetch,decode,execute,memory,writeBack).map(_.arbitration.isValid).orR)
|
||||
}
|
||||
}
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
#include "../common/framework.h"
|
||||
#include "../common/jtag.h"
|
||||
#include "../common/uart.h"
|
||||
|
||||
|
||||
|
||||
|
@ -214,62 +215,6 @@ public:
|
|||
}
|
||||
};
|
||||
|
||||
class UartRx : public SensitiveProcess{
|
||||
public:
|
||||
|
||||
CData *rx;
|
||||
uint32_t uartTimeRate;
|
||||
UartRx(CData *rx, uint32_t uartTimeRate){
|
||||
this->rx = rx;
|
||||
this->uartTimeRate = uartTimeRate;
|
||||
}
|
||||
|
||||
enum State {START, DATA, STOP,START_SUCCESS};
|
||||
State state = START;
|
||||
uint64_t holdTime = 0;
|
||||
CData holdValue;
|
||||
char data;
|
||||
uint32_t counter;
|
||||
virtual void tick(uint64_t time){
|
||||
if(time < holdTime){
|
||||
if(*rx != holdValue && time + (uartTimeRate>>7) < holdTime){
|
||||
cout << "UART RX FRAME ERROR at " << time << endl;
|
||||
holdTime = time;
|
||||
state = START;
|
||||
}
|
||||
}else{
|
||||
switch(state){
|
||||
case START:
|
||||
case START_SUCCESS:
|
||||
if(state == START_SUCCESS){
|
||||
cout << data << flush;
|
||||
state = START;
|
||||
}
|
||||
if(*rx == 0 && time > uartTimeRate){
|
||||
holdTime = time + uartTimeRate;
|
||||
holdValue = *rx;
|
||||
state = DATA;
|
||||
counter = 0;
|
||||
data = 0;
|
||||
}
|
||||
break;
|
||||
case DATA:
|
||||
data |= (*rx) << counter++;
|
||||
if(counter == 8){
|
||||
state = STOP;
|
||||
}
|
||||
holdValue = *rx;
|
||||
holdTime = time + uartTimeRate;
|
||||
break;
|
||||
case STOP:
|
||||
holdTime = time + uartTimeRate;
|
||||
holdValue = 1;
|
||||
state = START_SUCCESS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
class VexRiscvTracer : public SimElement{
|
||||
public:
|
||||
|
@ -432,12 +377,12 @@ public:
|
|||
ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000);
|
||||
AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000);
|
||||
Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,80000);
|
||||
UartRx *uartRx = new UartRx(&top->io_uart_txd,(50000000/8/115200)*8*axiClk->tooglePeriod*2);
|
||||
UartRx *uartRx = new UartRx(&top->io_uart_txd,1.0e12/115200);
|
||||
timeProcesses.push_back(axiClk);
|
||||
timeProcesses.push_back(vgaClk);
|
||||
timeProcesses.push_back(asyncReset);
|
||||
timeProcesses.push_back(jtag);
|
||||
checkProcesses.push_back(uartRx);
|
||||
timeProcesses.push_back(uartRx);
|
||||
|
||||
SdramConfig *sdramConfig = new SdramConfig(
|
||||
2, //byteCount
|
||||
|
|
|
@ -0,0 +1,111 @@
|
|||
|
||||
|
||||
|
||||
class UartRx : public TimeProcess{
|
||||
public:
|
||||
|
||||
CData *rx;
|
||||
uint32_t uartTimeRate;
|
||||
UartRx(CData *rx, uint32_t uartTimeRate){
|
||||
this->rx = rx;
|
||||
this->uartTimeRate = uartTimeRate;
|
||||
schedule(uartTimeRate);
|
||||
}
|
||||
|
||||
enum State {START, DATA, STOP,START_SUCCESS};
|
||||
State state = START;
|
||||
char data;
|
||||
uint32_t counter;
|
||||
|
||||
|
||||
virtual void tick(){
|
||||
switch(state){
|
||||
case START:
|
||||
if(*rx == 0){
|
||||
state = DATA;
|
||||
counter = 0;
|
||||
data = 0;
|
||||
schedule(uartTimeRate*5/4);
|
||||
} else {
|
||||
schedule(uartTimeRate/4);
|
||||
}
|
||||
break;
|
||||
case DATA:
|
||||
data |= (*rx) << counter++;
|
||||
if(counter == 8){
|
||||
state = STOP;
|
||||
}
|
||||
schedule(uartTimeRate);
|
||||
break;
|
||||
case STOP:
|
||||
if(*rx){
|
||||
cout << data << flush;
|
||||
} else {
|
||||
cout << "UART RX FRAME ERROR at " << time << endl;
|
||||
}
|
||||
|
||||
schedule(uartTimeRate/4);
|
||||
state = START;
|
||||
break;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
class UartRx : public SensitiveProcess{
|
||||
public:
|
||||
|
||||
CData *rx;
|
||||
uint32_t uartTimeRate;
|
||||
UartRx(CData *rx, uint32_t uartTimeRate){
|
||||
this->rx = rx;
|
||||
this->uartTimeRate = uartTimeRate;
|
||||
}
|
||||
|
||||
enum State {START, DATA, STOP,START_SUCCESS};
|
||||
State state = START;
|
||||
uint64_t holdTime = 0;
|
||||
CData holdValue;
|
||||
char data;
|
||||
uint32_t counter;
|
||||
virtual void tick(uint64_t time){
|
||||
if(time < holdTime){
|
||||
if(*rx != holdValue && time + (uartTimeRate>>7) < holdTime){
|
||||
cout << "UART RX FRAME ERROR at " << time << endl;
|
||||
holdTime = time;
|
||||
state = START;
|
||||
}
|
||||
}else{
|
||||
switch(state){
|
||||
case START:
|
||||
case START_SUCCESS:
|
||||
if(state == START_SUCCESS){
|
||||
cout << data << flush;
|
||||
state = START;
|
||||
}
|
||||
if(*rx == 0 && time > uartTimeRate){
|
||||
holdTime = time + uartTimeRate;
|
||||
holdValue = *rx;
|
||||
state = DATA;
|
||||
counter = 0;
|
||||
data = 0;
|
||||
}
|
||||
break;
|
||||
case DATA:
|
||||
data |= (*rx) << counter++;
|
||||
if(counter == 8){
|
||||
state = STOP;
|
||||
}
|
||||
holdValue = *rx;
|
||||
holdTime = time + uartTimeRate;
|
||||
break;
|
||||
case STOP:
|
||||
holdTime = time + uartTimeRate;
|
||||
holdValue = 1;
|
||||
state = START_SUCCESS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
};*/
|
|
@ -5,15 +5,18 @@
|
|||
|
||||
#include "../common/framework.h"
|
||||
#include "../common/jtag.h"
|
||||
#include "../common/uart.h"
|
||||
|
||||
class MuraxWorkspace : public Workspace<VMurax>{
|
||||
public:
|
||||
MuraxWorkspace() : Workspace("Murax"){
|
||||
ClockDomain *mainClk = new ClockDomain(&top->io_mainClk,NULL,83333,300000);
|
||||
AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000);
|
||||
UartRx *uartRx = new UartRx(&top->io_uart_txd,1.0e12/115200);
|
||||
|
||||
timeProcesses.push_back(mainClk);
|
||||
timeProcesses.push_back(asyncReset);
|
||||
timeProcesses.push_back(uartRx);
|
||||
|
||||
Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4);
|
||||
timeProcesses.push_back(jtag);
|
||||
|
|
|
@ -421,7 +421,7 @@ public:
|
|||
for(SimElement* simElement : simElements) simElement->preCycle();
|
||||
|
||||
if(withInstructionReadCheck){
|
||||
if(top->VexRiscv->decode_arbitration_isValid && !top->VexRiscv->decode_arbitration_haltIt){
|
||||
if(top->VexRiscv->decode_arbitration_isValid && !top->VexRiscv->decode_arbitration_haltItself){
|
||||
uint32_t expectedData;
|
||||
bool dummy;
|
||||
iBusAccess(top->VexRiscv->decode_PC, &expectedData, &dummy);
|
||||
|
|
Loading…
Reference in New Issue