CfuPlugin now only fork when the rest of the pipeline is hazard free

src/main/scala/vexriscv/Stage.scala

@@ -14,13 +14,13 @@ class Stageable[T <: Data](_dataType : => T) extends HardType[T](_dataType) with
 
 class Stage() extends Area{
   def outsideCondScope[T](that : => T) : T = {
-    val body = Component.current.dslBody
-    body.push()
-    val swapContext = body.swap()
-    val ret = that
-    body.pop()
-    swapContext.appendBack()
-    ret
+    val body = Component.current.dslBody  // Get the head of the current component symboles tree (AST in other words)
+    body.push()                           // Now all access to the SpinalHDL API will be append to it (instead of the current context)
+    val swapContext = body.swap()         // Empty the symbole tree (but keep a reference to the old content)
+    val ret = that                        // Execute the block of code (will be added to the recently empty body)
+    body.pop()                            // Restore the original context in which this function was called
+    swapContext.appendBack()              // append the original symboles tree to the modified body
+    ret                                   // return the value returned by that
   }
 
   def input[T <: Data](key : Stageable[T]) : T = {

src/main/scala/vexriscv/plugin/CfuPlugin.scala

@@ -166,7 +166,11 @@ class CfuPlugin(val stageCount : Int,
 
     forkStage plug new Area{
       import forkStage._
-      val schedule = arbitration.isValid && input(CFU_ENABLE)
+      val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
+      val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
+      val schedule = scheduleWish && !hazard
+      arbitration.haltItself setWhen(scheduleWish && hazard)
+
       val hold = RegInit(False) setWhen(schedule) clearWhen(bus.cmd.ready)
       val fired = RegInit(False) setWhen(bus.cmd.fire) clearWhen(!arbitration.isStuckByOthers)
       insert(CFU_IN_FLIGHT) := schedule || hold || fired

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -81,8 +81,9 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         //        REGFILE_WRITE_VALID -> True,
         //        BYPASSABLE_EXECUTE_STAGE -> False,
         //        BYPASSABLE_MEMORY_STAGE -> False,
-        MEMORY_WR -> False
-      ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
+        MEMORY_WR -> False,
+        HAS_SIDE_EFFECT -> True
+      )
     )
 
     if(withLrSc) decoderService.add(key, Seq(MEMORY_LRSC -> False))
@@ -103,8 +104,9 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB,
         SRC2_CTRL -> Src2CtrlEnum.IMS,
 //        RS2_USE -> True,
-        MEMORY_WR -> True
-      ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
+        MEMORY_WR -> True,
+        HAS_SIDE_EFFECT -> True
+      )
     )
 
     if(withLrSc) decoderService.add(key, Seq(MEMORY_LRSC -> False))
@@ -156,13 +158,15 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       REGFILE_WRITE_VALID -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE -> False,
-      MEMORY_WR -> False
-    ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
+      MEMORY_WR -> False,
+      HAS_SIDE_EFFECT -> True
+    )
 
     val storeActions = stdActions ++ List(
       SRC2_CTRL -> Src2CtrlEnum.IMS,
       RS2_USE -> True,
-      MEMORY_WR -> True
+      MEMORY_WR -> True,
+      HAS_SIDE_EFFECT -> True
     )
 
     decoderService.addDefault(MEMORY_ENABLE, False)

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -327,13 +327,15 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
       REGFILE_WRITE_VALID -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE  -> Bool(earlyInjection),
-      MEMORY_STORE -> False
-    ) ++ (if(catchAccessFault || catchAddressMisaligned) List(HAS_SIDE_EFFECT -> True) else Nil)
+      MEMORY_STORE -> False,
+      HAS_SIDE_EFFECT -> True
+    )
 
     val storeActions = stdActions ++ List(
       SRC2_CTRL -> Src2CtrlEnum.IMS,
       RS2_USE -> True,
-      MEMORY_STORE -> True
+      MEMORY_STORE -> True,
+      HAS_SIDE_EFFECT -> True
     )
 
     decoderService.addDefault(MEMORY_ENABLE, False)