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Update SynthesisBench murax

This commit is contained in:
Dolu1990 2018-05-24 14:03:28 +02:00
parent 6c47a3b2a3
commit c4f33b30e2
1 changed files with 5 additions and 4 deletions
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9
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -7,6 +7,7 @@ import vexriscv.VexRiscv
import vexriscv.plugin.{DecoderSimplePlugin, KeepAttribute} import vexriscv.plugin.{DecoderSimplePlugin, KeepAttribute}
import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.ArrayBuffer
import scala.util.Random
/** /**
* Created by PIC32F_USER on 16/07/2017. * Created by PIC32F_USER on 16/07/2017.
@ -105,7 +106,6 @@ object VexRiscvSynthesisBench {
// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
// val rtls = List(smallAndProductive, full) // val rtls = List(smallAndProductive, full)
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
) ++ AlteraStdTargets( ) ++ AlteraStdTargets(
@ -154,7 +154,7 @@ object MuraxSynthesisBench {
override def getName(): String = "Murax" override def getName(): String = "Murax"
override def getRtlPath(): String = "Murax.v" override def getRtlPath(): String = "Murax.v"
SpinalVerilog({ SpinalVerilog({
val murax = new Murax(MuraxConfig.default).setDefinitionName(getRtlPath().split("\\.").head) val murax = new Murax(MuraxConfig.default.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head)
murax.io.mainClk.setName("clk") murax.io.mainClk.setName("clk")
murax murax
}) })
@ -165,7 +165,7 @@ object MuraxSynthesisBench {
override def getName(): String = "MuraxFast" override def getName(): String = "MuraxFast"
override def getRtlPath(): String = "MuraxFast.v" override def getRtlPath(): String = "MuraxFast.v"
SpinalVerilog({ SpinalVerilog({
val murax = new Murax(MuraxConfig.fast).setDefinitionName(getRtlPath().split("\\.").head) val murax = new Murax(MuraxConfig.fast.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head)
murax.io.mainClk.setName("clk") murax.io.mainClk.setName("clk")
murax murax
}) })
@ -173,13 +173,14 @@ object MuraxSynthesisBench {
val rtls = List(murax, muraxFast) val rtls = List(murax, muraxFast)
val targets = XilinxStdTargets( val targets = IcestormStdTargets() ++ XilinxStdTargets(
vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
) ++ AlteraStdTargets( ) ++ AlteraStdTargets(
quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/", quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/",
quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/" quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/"
) )
Bench(rtls, targets, "/eda/tmp/") Bench(rtls, targets, "/eda/tmp/")
} }
} }