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VexRiscv
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Rework constructors

This commit is contained in:
Charles Papon 2017-05-01 20:20:21 +02:00
parent 889a040f90
commit c647ef8bb6
3 changed files with 209 additions and 212 deletions
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6
src/main/scala/SpinalRiscv/Plugin/PcManagerSimplePlugin.scala
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@ -34,7 +34,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
arbitration.isValid := True arbitration.isValid := True
//PC calculation without Jump //PC calculation without Jump
val pcReg = Reg(UInt(pcWidth bits)) init(resetVector) addAttribute(Verilator.public) val pcReg = Reg(UInt(32 bits)) init(resetVector) addAttribute(Verilator.public)
val inc = RegInit(False) val inc = RegInit(False)
val pcBeforeJumps = if(fastPcCalculation){ val pcBeforeJumps = if(fastPcCalculation){
val pcPlus4 = pcReg + U(4) val pcPlus4 = pcReg + U(4)
@ -45,7 +45,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
} }
insert(PC_CALC_WITHOUT_JUMP) := pcBeforeJumps insert(PC_CALC_WITHOUT_JUMP) := pcBeforeJumps
val pc = UInt(pcWidth bits) val pc = UInt(32 bits)
pc := input(PC_CALC_WITHOUT_JUMP) pc := input(PC_CALC_WITHOUT_JUMP)
val samplePcNext = False //TODO FMAX val samplePcNext = False //TODO FMAX
@ -56,7 +56,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
val valids = sortedByStage.map(_.interface.valid) val valids = sortedByStage.map(_.interface.valid)
val pcs = sortedByStage.map(_.interface.payload) val pcs = sortedByStage.map(_.interface.payload)
val pcLoad = Flow(UInt(pcWidth bits)) val pcLoad = Flow(UInt(32 bits))
pcLoad.valid := jumpInfos.map(_.interface.valid).orR pcLoad.valid := jumpInfos.map(_.interface.valid).orR
pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs) pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)

408
src/main/scala/SpinalRiscv/TopLevel.scala
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@ -26,9 +26,7 @@ import spinal.lib._
object TopLevel { object TopLevel {
def main(args: Array[String]) { def main(args: Array[String]) {
SpinalVerilog { SpinalVerilog {
val configFull = VexRiscvConfig(
pcWidth = 32
)
// val iCacheConfig = InstructionCacheConfig( // val iCacheConfig = InstructionCacheConfig(
// cacheSize =4096, // cacheSize =4096,
@ -98,221 +96,221 @@ object TopLevel {
wfiGen = false wfiGen = false
) )
configFull.plugins ++= List( val configFull = VexRiscvConfig(
new PcManagerSimplePlugin(0x00000000l, false), plugins = List(
new IBusSimplePlugin( new PcManagerSimplePlugin(0x00000000l, false),
interfaceKeepData = true, new IBusSimplePlugin(
catchAccessFault = true interfaceKeepData = true,
), catchAccessFault = true
// new IBusCachedPlugin( ),
// config = InstructionCacheConfig( // new IBusCachedPlugin(
// cacheSize = 4096, // config = InstructionCacheConfig(
// bytePerLine =32, // cacheSize = 4096,
// wayCount = 1, // bytePerLine =32,
// wrappedMemAccess = true, // wayCount = 1,
// addressWidth = 32, // wrappedMemAccess = true,
// cpuDataWidth = 32, // addressWidth = 32,
// memDataWidth = 32, // cpuDataWidth = 32,
// catchAccessFault = true, // memDataWidth = 32,
// asyncTagMemory = false, // catchAccessFault = true,
// twoStageLogic = true // asyncTagMemory = false,
// ) // twoStageLogic = true
// ), // )
// new DBusSimplePlugin( // ),
// catchAddressMisaligned = true, // new DBusSimplePlugin(
// catchAccessFault = true // catchAddressMisaligned = true,
// ), // catchAccessFault = true
new DBusCachedPlugin( // ),
config = new DataCacheConfig( new DBusCachedPlugin(
cacheSize = 4096, config = new DataCacheConfig(
bytePerLine = 32, cacheSize = 4096,
wayCount = 1, bytePerLine = 32,
addressWidth = 32, wayCount = 1,
cpuDataWidth = 32, addressWidth = 32,
memDataWidth = 32, cpuDataWidth = 32,
catchAccessFault = false, memDataWidth = 32,
catchMemoryTranslationMiss = false catchAccessFault = false,
catchMemoryTranslationMiss = false
)
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
),
new RegFilePlugin(
regFileReadyKind = Plugin.SYNC,
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false
),
new FullBarrielShifterPlugin,
// new LightShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
// new HazardSimplePlugin(false, true, false, true),
// new HazardSimplePlugin(false, false, false, false),
new MulPlugin,
new DivPlugin,
new MachineCsr(csrConfigAll),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = true,
prediction = DYNAMIC
) )
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
),
new RegFilePlugin(
regFileReadyKind = Plugin.SYNC,
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false
),
new FullBarrielShifterPlugin,
// new LightShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
// new HazardSimplePlugin(false, true, false, true),
// new HazardSimplePlugin(false, false, false, false),
new MulPlugin,
new DivPlugin,
new MachineCsr(csrConfigAll),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = true,
prediction = DYNAMIC
) )
) )
val configLight = VexRiscvConfig( val configLight = VexRiscvConfig(
pcWidth = 32 plugins = List(
) new PcManagerSimplePlugin(0x00000000l, false),
new IBusSimplePlugin(
interfaceKeepData = true,
catchAccessFault = false
),
configLight.plugins ++= List( new DBusSimplePlugin(
new PcManagerSimplePlugin(0x00000000l, false), catchAddressMisaligned = false,
new IBusSimplePlugin( catchAccessFault = false
interfaceKeepData = true, ),
catchAccessFault = false new DecoderSimplePlugin(
), catchIllegalInstruction = false
),
new DBusSimplePlugin( new RegFilePlugin(
catchAddressMisaligned = false, regFileReadyKind = Plugin.ASYNC,
catchAccessFault = false zeroBoot = false
), ),
new DecoderSimplePlugin( new IntAluPlugin,
catchIllegalInstruction = false new SrcPlugin(
), separatedAddSub = false
new RegFilePlugin( ),
regFileReadyKind = Plugin.ASYNC, // new FullBarrielShifterPlugin,
zeroBoot = false new LightShifterPlugin,
), // new HazardSimplePlugin(true, true, true, true),
new IntAluPlugin, // new HazardSimplePlugin(false, true, false, true),
new SrcPlugin( // new HazardSimplePlugin(
separatedAddSub = false // bypassExecute = false,
), // bypassMemory = false,
// new FullBarrielShifterPlugin, // bypassWriteBack = false,
new LightShifterPlugin, // bypassWriteBackBuffer = false,
// new HazardSimplePlugin(true, true, true, true), // pessimisticUseSrc = false,
// new HazardSimplePlugin(false, true, false, true), // pessimisticWriteRegFile = false,
// new HazardSimplePlugin( // pessimisticAddressMatch = false
// bypassExecute = false, // ),
// bypassMemory = false, new HazardPessimisticPlugin,
// bypassWriteBack = false, // new MulPlugin,
// bypassWriteBackBuffer = false, // new DivPlugin,
// pessimisticUseSrc = false, // new MachineCsr(csrConfig),
// pessimisticWriteRegFile = false, new BranchPlugin(
// pessimisticAddressMatch = false earlyBranch = false,
// ), catchAddressMisaligned = false,
new HazardPessimisticPlugin, prediction = NONE
// new MulPlugin, )
// new DivPlugin,
// new MachineCsr(csrConfig),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false,
prediction = NONE
) )
) )
val configTest = VexRiscvConfig( val configTest = VexRiscvConfig(
pcWidth = 32 plugins = List(
) new PcManagerSimplePlugin(0x00000000l, true),
// new IBusSimplePlugin(
configTest.plugins ++= List( // interfaceKeepData = true,
new PcManagerSimplePlugin(0x00000000l, true), // catchAccessFault = false
// new IBusSimplePlugin( // ),
// interfaceKeepData = true, new IBusCachedPlugin(
// catchAccessFault = false config = InstructionCacheConfig(
// ), cacheSize = 4096,
new IBusCachedPlugin( bytePerLine =32,
config = InstructionCacheConfig( wayCount = 1,
cacheSize = 4096, wrappedMemAccess = true,
bytePerLine =32, addressWidth = 32,
wayCount = 1, cpuDataWidth = 32,
wrappedMemAccess = true, memDataWidth = 32,
addressWidth = 32, catchAccessFault = false,
cpuDataWidth = 32, asyncTagMemory = false,
memDataWidth = 32, twoStageLogic = true
catchAccessFault = false, )
asyncTagMemory = false,
twoStageLogic = true
)
),
// new DBusSimplePlugin(
// catchAddressMisaligned = false,
// catchAccessFault = false
// ),
// new DBusCachedPlugin(
// config = new DataCacheConfig(
// cacheSize = 2048,
// bytePerLine = 32,
// wayCount = 1,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessFault = false
// )
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = false,
catchMemoryTranslationMiss = true,
tagSizeShift = 2
), ),
askMemoryTranslation = true,
memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
portTlbSize = 6
)
),
new MemoryTranslatorPlugin( // new DBusSimplePlugin(
tlbSize = 32, // catchAddressMisaligned = false,
mmuRange = _(31 downto 28) === 0xC // catchAccessFault = false
), // ),
new MachineCsr(csrConfigSmall), // new DBusCachedPlugin(
new DecoderSimplePlugin( // config = new DataCacheConfig(
catchIllegalInstruction = false // cacheSize = 2048,
), // bytePerLine = 32,
new RegFilePlugin( // wayCount = 1,
regFileReadyKind = Plugin.SYNC, // addressWidth = 32,
zeroBoot = true // cpuDataWidth = 32,
), // memDataWidth = 32,
new IntAluPlugin, // catchAccessFault = false
new SrcPlugin( // )
separatedAddSub = false // ),
), new DBusCachedPlugin(
new FullBarrielShifterPlugin, config = new DataCacheConfig(
// new LightShifterPlugin, cacheSize = 4096,
// new HazardSimplePlugin(true, true, true, true), bytePerLine = 32,
// new HazardSimplePlugin(false, true, false, true), wayCount = 1,
new HazardSimplePlugin( addressWidth = 32,
bypassExecute = false, cpuDataWidth = 32,
bypassMemory = false, memDataWidth = 32,
bypassWriteBack = false, catchAccessFault = false,
bypassWriteBackBuffer = false, catchMemoryTranslationMiss = true,
pessimisticUseSrc = false, tagSizeShift = 2
pessimisticWriteRegFile = false, ),
pessimisticAddressMatch = false askMemoryTranslation = true,
), memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// new MulPlugin, portTlbSize = 6
// new DivPlugin, )
// new MachineCsr(csrConfig), ),
new BranchPlugin(
earlyBranch = false, new MemoryTranslatorPlugin(
catchAddressMisaligned = false, tlbSize = 32,
prediction = NONE mmuRange = _(31 downto 28) === 0xC
),
new MachineCsr(csrConfigSmall),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = Plugin.SYNC,
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false
),
new FullBarrielShifterPlugin,
// new LightShifterPlugin,
// new HazardSimplePlugin(true, true, true, true),
// new HazardSimplePlugin(false, true, false, true),
new HazardSimplePlugin(
bypassExecute = false,
bypassMemory = false,
bypassWriteBack = false,
bypassWriteBackBuffer = false,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
// new MulPlugin,
// new DivPlugin,
// new MachineCsr(csrConfig),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = false,
prediction = NONE
)
) )
) )

7
src/main/scala/SpinalRiscv/VexRiscv.scala
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@ -5,8 +5,7 @@ import spinal.core._
import spinal.lib._ import spinal.lib._
import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.ArrayBuffer
case class VexRiscvConfig(pcWidth : Int){ case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
val plugins = ArrayBuffer[Plugin[VexRiscv]]()
//Default Stageables //Default Stageables
object BYPASSABLE_EXECUTE_STAGE extends Stageable(Bool) object BYPASSABLE_EXECUTE_STAGE extends Stageable(Bool)
@ -16,8 +15,8 @@ case class VexRiscvConfig(pcWidth : Int){
object REG1_USE extends Stageable(Bool) object REG1_USE extends Stageable(Bool)
object REG2_USE extends Stageable(Bool) object REG2_USE extends Stageable(Bool)
object RESULT extends Stageable(UInt(32 bits)) object RESULT extends Stageable(UInt(32 bits))
object PC extends Stageable(UInt(pcWidth bits)) object PC extends Stageable(UInt(32 bits))
object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(pcWidth bits)) object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(32 bits))
object INSTRUCTION extends Stageable(Bits(32 bits)) object INSTRUCTION extends Stageable(Bits(32 bits))
object INSTRUCTION_READY extends Stageable(Bool) object INSTRUCTION_READY extends Stageable(Bool)
object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits)) object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits))