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VexRiscv
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Rework constructors

This commit is contained in:
Charles Papon 2017-05-01 20:20:21 +02:00
parent 889a040f90
commit c647ef8bb6
3 changed files with 209 additions and 212 deletions
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6
src/main/scala/SpinalRiscv/Plugin/PcManagerSimplePlugin.scala
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@ -34,7 +34,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
arbitration.isValid := True
//PC calculation without Jump
val pcReg = Reg(UInt(pcWidth bits)) init(resetVector) addAttribute(Verilator.public)
val pcReg = Reg(UInt(32 bits)) init(resetVector) addAttribute(Verilator.public)
val inc = RegInit(False)
val pcBeforeJumps = if(fastPcCalculation){
val pcPlus4 = pcReg + U(4)
@ -45,7 +45,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
}
insert(PC_CALC_WITHOUT_JUMP) := pcBeforeJumps
val pc = UInt(pcWidth bits)
val pc = UInt(32 bits)
pc := input(PC_CALC_WITHOUT_JUMP)
val samplePcNext = False //TODO FMAX
@ -56,7 +56,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
val valids = sortedByStage.map(_.interface.valid)
val pcs = sortedByStage.map(_.interface.payload)
val pcLoad = Flow(UInt(pcWidth bits))
val pcLoad = Flow(UInt(32 bits))
pcLoad.valid := jumpInfos.map(_.interface.valid).orR
pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)

22
src/main/scala/SpinalRiscv/TopLevel.scala
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@ -26,9 +26,7 @@ import spinal.lib._
object TopLevel {
def main(args: Array[String]) {
SpinalVerilog {
val configFull = VexRiscvConfig(
pcWidth = 32
)
// val iCacheConfig = InstructionCacheConfig(
// cacheSize =4096,
@ -98,7 +96,8 @@ object TopLevel {
wfiGen = false
)
configFull.plugins ++= List(
val configFull = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(0x00000000l, false),
new IBusSimplePlugin(
interfaceKeepData = true,
@ -167,12 +166,11 @@ object TopLevel {
prediction = DYNAMIC
)
)
val configLight = VexRiscvConfig(
pcWidth = 32
)
configLight.plugins ++= List(
val configLight = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(0x00000000l, false),
new IBusSimplePlugin(
interfaceKeepData = true,
@ -217,13 +215,12 @@ object TopLevel {
prediction = NONE
)
)
)
val configTest = VexRiscvConfig(
pcWidth = 32
)
configTest.plugins ++= List(
plugins = List(
new PcManagerSimplePlugin(0x00000000l, true),
// new IBusSimplePlugin(
// interfaceKeepData = true,
@ -315,6 +312,7 @@ object TopLevel {
prediction = NONE
)
)
)
// val toplevel = new VexRiscv(configFull)
// val toplevel = new VexRiscv(configLight)

7
src/main/scala/SpinalRiscv/VexRiscv.scala
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@ -5,8 +5,7 @@ import spinal.core._
import spinal.lib._
import scala.collection.mutable.ArrayBuffer
case class VexRiscvConfig(pcWidth : Int){
val plugins = ArrayBuffer[Plugin[VexRiscv]]()
case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
//Default Stageables
object BYPASSABLE_EXECUTE_STAGE extends Stageable(Bool)
@ -16,8 +15,8 @@ case class VexRiscvConfig(pcWidth : Int){
object REG1_USE extends Stageable(Bool)
object REG2_USE extends Stageable(Bool)
object RESULT extends Stageable(UInt(32 bits))
object PC extends Stageable(UInt(pcWidth bits))
object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(pcWidth bits))
object PC extends Stageable(UInt(32 bits))
object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(32 bits))
object INSTRUCTION extends Stageable(Bits(32 bits))
object INSTRUCTION_READY extends Stageable(Bool)
object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits))