Rework constructors
This commit is contained in:
Charles Papon
parent
889a040f90
commit
c647ef8bb6
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@ -34,7 +34,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
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arbitration.isValid := True
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//PC calculation without Jump
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val pcReg = Reg(UInt(pcWidth bits)) init(resetVector) addAttribute(Verilator.public)
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val pcReg = Reg(UInt(32 bits)) init(resetVector) addAttribute(Verilator.public)
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val inc = RegInit(False)
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val pcBeforeJumps = if(fastPcCalculation){
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val pcPlus4 = pcReg + U(4)
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@ -45,7 +45,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
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}
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insert(PC_CALC_WITHOUT_JUMP) := pcBeforeJumps
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val pc = UInt(pcWidth bits)
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val pc = UInt(32 bits)
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pc := input(PC_CALC_WITHOUT_JUMP)
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val samplePcNext = False //TODO FMAX
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@ -56,7 +56,7 @@ class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) e
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val valids = sortedByStage.map(_.interface.valid)
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val pcs = sortedByStage.map(_.interface.payload)
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val pcLoad = Flow(UInt(pcWidth bits))
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val pcLoad = Flow(UInt(32 bits))
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pcLoad.valid := jumpInfos.map(_.interface.valid).orR
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pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)
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@ -26,9 +26,7 @@ import spinal.lib._
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object TopLevel {
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def main(args: Array[String]) {
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SpinalVerilog {
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val configFull = VexRiscvConfig(
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pcWidth = 32
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)
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// val iCacheConfig = InstructionCacheConfig(
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// cacheSize =4096,
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@ -98,221 +96,221 @@ object TopLevel {
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wfiGen = false
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)
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configFull.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true,
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catchAccessFault = true
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),
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine =32,
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// wayCount = 1,
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// wrappedMemAccess = true,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessFault = true,
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// asyncTagMemory = false,
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// twoStageLogic = true
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// )
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// ),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = true
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessFault = false,
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catchMemoryTranslationMiss = false
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val configFull = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true,
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catchAccessFault = true
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),
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine =32,
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// wayCount = 1,
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// wrappedMemAccess = true,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessFault = true,
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// asyncTagMemory = false,
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// twoStageLogic = true
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// )
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// ),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// catchAccessFault = true
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessFault = false,
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catchMemoryTranslationMiss = false
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)
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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new MulPlugin,
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new DivPlugin,
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new MachineCsr(csrConfigAll),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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)
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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new MulPlugin,
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new DivPlugin,
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new MachineCsr(csrConfigAll),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = DYNAMIC
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)
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)
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val configLight = VexRiscvConfig(
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pcWidth = 32
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)
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true,
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catchAccessFault = false
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),
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configLight.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.ASYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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// new FullBarrielShifterPlugin,
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new LightShifterPlugin,
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// new HazardSimplePlugin(true, true, true, true),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(
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// bypassExecute = false,
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// bypassMemory = false,
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// bypassWriteBack = false,
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// bypassWriteBackBuffer = false,
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// pessimisticUseSrc = false,
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// pessimisticWriteRegFile = false,
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// pessimisticAddressMatch = false
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// ),
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new HazardPessimisticPlugin,
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// new MulPlugin,
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// new DivPlugin,
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// new MachineCsr(csrConfig),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.ASYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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// new FullBarrielShifterPlugin,
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new LightShifterPlugin,
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// new HazardSimplePlugin(true, true, true, true),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(
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// bypassExecute = false,
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// bypassMemory = false,
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// bypassWriteBack = false,
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// bypassWriteBackBuffer = false,
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// pessimisticUseSrc = false,
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// pessimisticWriteRegFile = false,
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// pessimisticAddressMatch = false
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// ),
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new HazardPessimisticPlugin,
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// new MulPlugin,
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// new DivPlugin,
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// new MachineCsr(csrConfig),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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)
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)
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)
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val configTest = VexRiscvConfig(
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pcWidth = 32
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)
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configTest.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, true),
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// new IBusSimplePlugin(
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// interfaceKeepData = true,
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// catchAccessFault = false
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessFault = false,
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asyncTagMemory = false,
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twoStageLogic = true
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)
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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// new DBusCachedPlugin(
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// config = new DataCacheConfig(
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// cacheSize = 2048,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessFault = false
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// )
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessFault = false,
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catchMemoryTranslationMiss = true,
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tagSizeShift = 2
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, true),
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// new IBusSimplePlugin(
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// interfaceKeepData = true,
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// catchAccessFault = false
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessFault = false,
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asyncTagMemory = false,
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twoStageLogic = true
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)
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),
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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mmuRange = _(31 downto 28) === 0xC
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),
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new MachineCsr(csrConfigSmall),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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// new HazardSimplePlugin(true, true, true, true),
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// new HazardSimplePlugin(false, true, false, true),
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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// new MulPlugin,
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// new DivPlugin,
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// new MachineCsr(csrConfig),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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// new DBusCachedPlugin(
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// config = new DataCacheConfig(
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// cacheSize = 2048,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessFault = false
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// )
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessFault = false,
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catchMemoryTranslationMiss = true,
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tagSizeShift = 2
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),
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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mmuRange = _(31 downto 28) === 0xC
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),
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new MachineCsr(csrConfigSmall),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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// new HazardSimplePlugin(true, true, true, true),
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// new HazardSimplePlugin(false, true, false, true),
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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// new MulPlugin,
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// new DivPlugin,
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// new MachineCsr(csrConfig),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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)
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)
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)
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|
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@ -5,8 +5,7 @@ import spinal.core._
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import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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case class VexRiscvConfig(pcWidth : Int){
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val plugins = ArrayBuffer[Plugin[VexRiscv]]()
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case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){
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//Default Stageables
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object BYPASSABLE_EXECUTE_STAGE extends Stageable(Bool)
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@ -16,8 +15,8 @@ case class VexRiscvConfig(pcWidth : Int){
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object REG1_USE extends Stageable(Bool)
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object REG2_USE extends Stageable(Bool)
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object RESULT extends Stageable(UInt(32 bits))
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object PC extends Stageable(UInt(pcWidth bits))
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object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(pcWidth bits))
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object PC extends Stageable(UInt(32 bits))
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object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(32 bits))
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object INSTRUCTION extends Stageable(Bits(32 bits))
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object INSTRUCTION_READY extends Stageable(Bool)
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object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits))
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