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VexRiscv
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Got buildroot login, userspace, commands working 

Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
This commit is contained in:
Charles Papon 2019-03-31 15:17:45 +02:00
parent de500ad8f9
commit c7314cc606
11 changed files with 715 additions and 477 deletions
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900
src/main/c/emulator/build/emulator.asm
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@ -6,33 +6,33 @@ Disassembly of section .init:
80000000 <_start>: 80000000 <_start>:
80000000: 00001117 auipc sp,0x1 80000000: 00001117 auipc sp,0x1
80000004: 00810113 addi sp,sp,8 # 80001008 <_sp> 80000004: 11010113 addi sp,sp,272 # 80001110 <_sp>
80000008: 00000517 auipc a0,0x0 80000008: 00001517 auipc a0,0x1
8000000c: 78c50513 addi a0,a0,1932 # 80000794 <__init_array_end> 8000000c: 86450513 addi a0,a0,-1948 # 8000086c <__init_array_end>
80000010: 00000597 auipc a1,0x0 80000010: 00001597 auipc a1,0x1
80000014: 78458593 addi a1,a1,1924 # 80000794 <__init_array_end> 80000014: 85c58593 addi a1,a1,-1956 # 8000086c <__init_array_end>
80000018: 00000617 auipc a2,0x0 80000018: 00001617 auipc a2,0x1
8000001c: 7f060613 addi a2,a2,2032 # 80000808 <__bss_start> 8000001c: 8f860613 addi a2,a2,-1800 # 80000910 <__bss_start>
80000020: 00c5fc63 bgeu a1,a2,80000038 <_start+0x38> 80000020: 00c5fc63 bgeu a1,a2,80000038 <_start+0x38>
80000024: 00052283 lw t0,0(a0) 80000024: 00052283 lw t0,0(a0)
80000028: 0055a023 sw t0,0(a1) 80000028: 0055a023 sw t0,0(a1)
8000002c: 00450513 addi a0,a0,4 8000002c: 00450513 addi a0,a0,4
80000030: 00458593 addi a1,a1,4 80000030: 00458593 addi a1,a1,4
80000034: fec5e8e3 bltu a1,a2,80000024 <_start+0x24> 80000034: fec5e8e3 bltu a1,a2,80000024 <_start+0x24>
80000038: 00000517 auipc a0,0x0 80000038: 00001517 auipc a0,0x1
8000003c: 7d050513 addi a0,a0,2000 # 80000808 <__bss_start> 8000003c: 8d850513 addi a0,a0,-1832 # 80000910 <__bss_start>
80000040: 00000597 auipc a1,0x0 80000040: 00001597 auipc a1,0x1
80000044: 7c858593 addi a1,a1,1992 # 80000808 <__bss_start> 80000044: 8d058593 addi a1,a1,-1840 # 80000910 <__bss_start>
80000048: 00b57863 bgeu a0,a1,80000058 <_start+0x58> 80000048: 00b57863 bgeu a0,a1,80000058 <_start+0x58>
8000004c: 00052023 sw zero,0(a0) 8000004c: 00052023 sw zero,0(a0)
80000050: 00450513 addi a0,a0,4 80000050: 00450513 addi a0,a0,4
80000054: feb56ce3 bltu a0,a1,8000004c <_start+0x4c> 80000054: feb56ce3 bltu a0,a1,8000004c <_start+0x4c>
80000058: 694000ef jal ra,800006ec <__libc_init_array> 80000058: 76c000ef jal ra,800007c4 <__libc_init_array>
8000005c: 120000ef jal ra,8000017c <init> 8000005c: 17c000ef jal ra,800001d8 <init>
80000060: 00000097 auipc ra,0x0 80000060: 00000097 auipc ra,0x0
80000064: 01408093 addi ra,ra,20 # 80000074 <done> 80000064: 01408093 addi ra,ra,20 # 80000074 <done>
80000068: 00000513 li a0,0 80000068: 00000513 li a0,0
8000006c: 810005b7 lui a1,0x81000 8000006c: c40005b7 lui a1,0xc4000
80000070: 30200073 mret 80000070: 30200073 mret
80000074 <done>: 80000074 <done>:
@ -73,7 +73,7 @@ Disassembly of section .init:
800000ec: 07d12a23 sw t4,116(sp) 800000ec: 07d12a23 sw t4,116(sp)
800000f0: 07e12c23 sw t5,120(sp) 800000f0: 07e12c23 sw t5,120(sp)
800000f4: 07f12e23 sw t6,124(sp) 800000f4: 07f12e23 sw t6,124(sp)
800000f8: 1f4000ef jal ra,800002ec <trap> 800000f8: 2c4000ef jal ra,800003bc <trap>
800000fc: 00412083 lw ra,4(sp) 800000fc: 00412083 lw ra,4(sp)
80000100: 00c12183 lw gp,12(sp) 80000100: 00c12183 lw gp,12(sp)
80000104: 01012203 lw tp,16(sp) 80000104: 01012203 lw tp,16(sp)
@ -109,420 +109,482 @@ Disassembly of section .init:
Disassembly of section .text: Disassembly of section .text:
8000017c <init>: 8000017c <putString>:
8000017c: 800007b7 lui a5,0x80000 8000017c: ff010113 addi sp,sp,-16
80000180: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff074> 80000180: 00812423 sw s0,8(sp)
80000184: 30579073 csrw mtvec,a5 80000184: 00112623 sw ra,12(sp)
80000188: 800017b7 lui a5,0x80001 80000188: 00050413 mv s0,a0
8000018c: f8878793 addi a5,a5,-120 # 80000f88 <_sp+0xffffff80> 8000018c: 00054503 lbu a0,0(a0)
80000190: 34079073 csrw mscratch,a5 80000190: 00050a63 beqz a0,800001a4 <putString+0x28>
80000194: 000017b7 lui a5,0x1 80000194: 00140413 addi s0,s0,1
80000198: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80> 80000198: 5f0000ef jal ra,80000788 <putC>
8000019c: 30079073 csrw mstatus,a5 8000019c: 00044503 lbu a0,0(s0)
800001a0: 30405073 csrwi mie,0 800001a0: fe051ae3 bnez a0,80000194 <putString+0x18>
800001a4: c00007b7 lui a5,0xc0000 800001a4: 00c12083 lw ra,12(sp)
800001a8: 34179073 csrw mepc,a5 800001a8: 00812403 lw s0,8(sp)
800001ac: 0000b7b7 lui a5,0xb 800001ac: 01010113 addi sp,sp,16
800001b0: 10078793 addi a5,a5,256 # b100 <__stack_size+0xa900> 800001b0: 00008067 ret
800001b4: 30279073 csrw medeleg,a5
800001b8: 22200793 li a5,546
800001bc: 30379073 csrw mideleg,a5
800001c0: 14305073 csrwi stval,0
800001c4: 00008067 ret
800001c8 <readRegister>: 800001b4 <setup_pmp>:
800001c8: 800017b7 lui a5,0x80001 800001b4: 01f00793 li a5,31
800001cc: f8878793 addi a5,a5,-120 # 80000f88 <_sp+0xffffff80> 800001b8: fff00713 li a4,-1
800001d0: 00251513 slli a0,a0,0x2 800001bc: 00000297 auipc t0,0x0
800001d4: 00f50533 add a0,a0,a5 800001c0: 01428293 addi t0,t0,20 # 800001d0 <setup_pmp+0x1c>
800001d8: 00052503 lw a0,0(a0) 800001c4: 305292f3 csrrw t0,mtvec,t0
800001dc: 00008067 ret 800001c8: 3b071073 csrw pmpaddr0,a4
800001cc: 3a079073 csrw pmpcfg0,a5
800001d0: 30529073 csrw mtvec,t0
800001d4: 00008067 ret
800001e0 <writeRegister>: 800001d8 <init>:
800001e0: 800017b7 lui a5,0x80001 800001d8: ff010113 addi sp,sp,-16
800001e4: 00251513 slli a0,a0,0x2 800001dc: 00112623 sw ra,12(sp)
800001e8: f8878793 addi a5,a5,-120 # 80000f88 <_sp+0xffffff80> 800001e0: 00812423 sw s0,8(sp)
800001ec: 00f50533 add a0,a0,a5 800001e4: 01f00793 li a5,31
800001f0: 00b52023 sw a1,0(a0) 800001e8: fff00713 li a4,-1
800001f4: 00008067 ret 800001ec: 00000297 auipc t0,0x0
800001f0: 01428293 addi t0,t0,20 # 80000200 <init+0x28>
800001f4: 305292f3 csrrw t0,mtvec,t0
800001f8: 3b071073 csrw pmpaddr0,a4
800001fc: 3a079073 csrw pmpcfg0,a5
80000200: 30529073 csrw mtvec,t0
80000204: 80001437 lui s0,0x80001
80000208: 5b8000ef jal ra,800007c0 <halInit>
8000020c: 8e040413 addi s0,s0,-1824 # 800008e0 <_sp+0xfffff7d0>
80000210: 02a00513 li a0,42
80000214: 00140413 addi s0,s0,1
80000218: 570000ef jal ra,80000788 <putC>
8000021c: 00044503 lbu a0,0(s0)
80000220: fe051ae3 bnez a0,80000214 <init+0x3c>
80000224: 800007b7 lui a5,0x80000
80000228: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef6c>
8000022c: 30579073 csrw mtvec,a5
80000230: 800017b7 lui a5,0x80001
80000234: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
80000238: 34079073 csrw mscratch,a5
8000023c: 000017b7 lui a5,0x1
80000240: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
80000244: 30079073 csrw mstatus,a5
80000248: 30405073 csrwi mie,0
8000024c: c00007b7 lui a5,0xc0000
80000250: 34179073 csrw mepc,a5
80000254: 0000b7b7 lui a5,0xb
80000258: 10078793 addi a5,a5,256 # b100 <__stack_size+0xa900>
8000025c: 30279073 csrw medeleg,a5
80000260: 22200793 li a5,546
80000264: 30379073 csrw mideleg,a5
80000268: 14305073 csrwi stval,0
8000026c: 80001437 lui s0,0x80001
80000270: 8f840413 addi s0,s0,-1800 # 800008f8 <_sp+0xfffff7e8>
80000274: 02a00513 li a0,42
80000278: 00140413 addi s0,s0,1
8000027c: 50c000ef jal ra,80000788 <putC>
80000280: 00044503 lbu a0,0(s0)
80000284: fe051ae3 bnez a0,80000278 <init+0xa0>
80000288: 00c12083 lw ra,12(sp)
8000028c: 00812403 lw s0,8(sp)
80000290: 01010113 addi sp,sp,16
80000294: 00008067 ret
800001f8 <redirectTrap>: 80000298 <readRegister>:
800001f8: ff010113 addi sp,sp,-16 80000298: 800017b7 lui a5,0x80001
800001fc: 00112623 sw ra,12(sp) 8000029c: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
80000200: 4b4000ef jal ra,800006b4 <stopSim> 800002a0: 00251513 slli a0,a0,0x2
80000204: 343027f3 csrr a5,mtval 800002a4: 00f50533 add a0,a0,a5
80000208: 14379073 csrw stval,a5 800002a8: 00052503 lw a0,0(a0)
8000020c: 341027f3 csrr a5,mepc 800002ac: 00008067 ret
80000210: 14179073 csrw sepc,a5
80000214: 342027f3 csrr a5,mcause
80000218: 14279073 csrw scause,a5
8000021c: 105027f3 csrr a5,stvec
80000220: 34179073 csrw mepc,a5
80000224: 00c12083 lw ra,12(sp)
80000228: 01010113 addi sp,sp,16
8000022c: 00008067 ret
80000230 <emulationTrapToSupervisorTrap>: 800002b0 <writeRegister>:
80000230: 800007b7 lui a5,0x80000 800002b0: 800017b7 lui a5,0x80001
80000234: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff074> 800002b4: 00251513 slli a0,a0,0x2
80000238: 30579073 csrw mtvec,a5 800002b8: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
8000023c: 343027f3 csrr a5,mtval 800002bc: 00f50533 add a0,a0,a5
80000240: 14379073 csrw stval,a5 800002c0: 00b52023 sw a1,0(a0)
80000244: 342027f3 csrr a5,mcause 800002c4: 00008067 ret
80000248: 14279073 csrw scause,a5
8000024c: 14151073 csrw sepc,a0
80000250: 105027f3 csrr a5,stvec
80000254: 34179073 csrw mepc,a5
80000258: 10000793 li a5,256
8000025c: 1007b073 csrc sstatus,a5
80000260: 0035d593 srli a1,a1,0x3
80000264: 1005f593 andi a1,a1,256
80000268: 1005a073 csrs sstatus,a1
8000026c: 000027b7 lui a5,0x2
80000270: 80078793 addi a5,a5,-2048 # 1800 <__stack_size+0x1000>
80000274: 3007b073 csrc mstatus,a5
80000278: 000017b7 lui a5,0x1
8000027c: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
80000280: 3007a073 csrs mstatus,a5
80000284: 00008067 ret
80000288 <readWord>: 800002c8 <redirectTrap>:
80000288: 00020737 lui a4,0x20 800002c8: ff010113 addi sp,sp,-16
8000028c: 30072073 csrs mstatus,a4 800002cc: 00112623 sw ra,12(sp)
80000290: 00000717 auipc a4,0x0 800002d0: 4b0000ef jal ra,80000780 <stopSim>
80000294: 01870713 addi a4,a4,24 # 800002a8 <readWord+0x20> 800002d4: 343027f3 csrr a5,mtval
80000298: 30571073 csrw mtvec,a4 800002d8: 14379073 csrw stval,a5
8000029c: 00100693 li a3,1 800002dc: 341027f3 csrr a5,mepc
800002a0: 00052783 lw a5,0(a0) 800002e0: 14179073 csrw sepc,a5
800002a4: 00000693 li a3,0 800002e4: 342027f3 csrr a5,mcause
800002a8: 00020737 lui a4,0x20 800002e8: 14279073 csrw scause,a5
800002ac: 30073073 csrc mstatus,a4 800002ec: 105027f3 csrr a5,stvec
800002b0: 00068513 mv a0,a3 800002f0: 34179073 csrw mepc,a5
800002b4: 00f5a023 sw a5,0(a1) # 81000000 <_sp+0xffeff8> 800002f4: 00c12083 lw ra,12(sp)
800002b8: 00008067 ret 800002f8: 01010113 addi sp,sp,16
800002fc: 00008067 ret
800002bc <writeWord>: 80000300 <emulationTrapToSupervisorTrap>:
800002bc: 00020737 lui a4,0x20 80000300: 800007b7 lui a5,0x80000
800002c0: 30072073 csrs mstatus,a4 80000304: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xffffef6c>
800002c4: 00000717 auipc a4,0x0 80000308: 30579073 csrw mtvec,a5
800002c8: 01870713 addi a4,a4,24 # 800002dc <writeWord+0x20> 8000030c: 343027f3 csrr a5,mtval
800002cc: 30571073 csrw mtvec,a4 80000310: 14379073 csrw stval,a5
800002d0: 00100793 li a5,1 80000314: 342027f3 csrr a5,mcause
800002d4: 00b52023 sw a1,0(a0) 80000318: 14279073 csrw scause,a5
800002d8: 00000793 li a5,0 8000031c: 14151073 csrw sepc,a0
800002dc: 00020737 lui a4,0x20 80000320: 105027f3 csrr a5,stvec
800002e0: 30073073 csrc mstatus,a4 80000324: 34179073 csrw mepc,a5
800002e4: 00078513 mv a0,a5 80000328: 10000793 li a5,256
800002e8: 00008067 ret 8000032c: 1007b073 csrc sstatus,a5
80000330: 0035d593 srli a1,a1,0x3
80000334: 1005f593 andi a1,a1,256
80000338: 1005a073 csrs sstatus,a1
8000033c: 000027b7 lui a5,0x2
80000340: 80078793 addi a5,a5,-2048 # 1800 <__stack_size+0x1000>
80000344: 3007b073 csrc mstatus,a5
80000348: 000017b7 lui a5,0x1
8000034c: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
80000350: 3007a073 csrs mstatus,a5
80000354: 00008067 ret
800002ec <trap>: 80000358 <readWord>:
800002ec: fe010113 addi sp,sp,-32 80000358: 00020737 lui a4,0x20
800002f0: 00112e23 sw ra,28(sp) 8000035c: 30072073 csrs mstatus,a4
800002f4: 00812c23 sw s0,24(sp) 80000360: 00000717 auipc a4,0x0
800002f8: 00912a23 sw s1,20(sp) 80000364: 01870713 addi a4,a4,24 # 80000378 <readWord+0x20>
800002fc: 01212823 sw s2,16(sp) 80000368: 30571073 csrw mtvec,a4
80000300: 01312623 sw s3,12(sp) 8000036c: 00100693 li a3,1
80000304: 342027f3 csrr a5,mcause 80000370: 00052783 lw a5,0(a0)
80000308: 0807cc63 bltz a5,800003a0 <trap+0xb4> 80000374: 00000693 li a3,0
8000030c: 00200713 li a4,2 80000378: 00020737 lui a4,0x20
80000310: 0ce78463 beq a5,a4,800003d8 <trap+0xec> 8000037c: 30073073 csrc mstatus,a4
80000314: 00900693 li a3,9 80000380: 00068513 mv a0,a3
80000318: 04d79463 bne a5,a3,80000360 <trap+0x74> 80000384: 00f5a023 sw a5,0(a1) # c4000000 <_sp+0x43ffeef0>
8000031c: 800017b7 lui a5,0x80001 80000388: 00008067 ret
80000320: 00878793 addi a5,a5,8 # 80001008 <_sp+0x0>
80000324: fc47a683 lw a3,-60(a5)
80000328: 00100613 li a2,1
8000032c: fa87a503 lw a0,-88(a5)
80000330: 2ec68663 beq a3,a2,8000061c <trap+0x330>
80000334: 2ae68463 beq a3,a4,800005dc <trap+0x2f0>
80000338: 2a068e63 beqz a3,800005f4 <trap+0x308>
8000033c: 01812403 lw s0,24(sp)
80000340: 01c12083 lw ra,28(sp)
80000344: 01412483 lw s1,20(sp)
80000348: 01012903 lw s2,16(sp)
8000034c: 00c12983 lw s3,12(sp)
80000350: 02010113 addi sp,sp,32
80000354: 3600006f j 800006b4 <stopSim>
80000358: 00777713 andi a4,a4,7
8000035c: 14f70063 beq a4,a5,8000049c <trap+0x1b0>
80000360: 354000ef jal ra,800006b4 <stopSim>
80000364: 343027f3 csrr a5,mtval
80000368: 14379073 csrw stval,a5
8000036c: 341027f3 csrr a5,mepc
80000370: 14179073 csrw sepc,a5
80000374: 342027f3 csrr a5,mcause
80000378: 14279073 csrw scause,a5
8000037c: 105027f3 csrr a5,stvec
80000380: 34179073 csrw mepc,a5
80000384: 01c12083 lw ra,28(sp)
80000388: 01812403 lw s0,24(sp)
8000038c: 01412483 lw s1,20(sp)
80000390: 01012903 lw s2,16(sp)
80000394: 00c12983 lw s3,12(sp)
80000398: 02010113 addi sp,sp,32
8000039c: 00008067 ret
800003a0: 0ff7f793 andi a5,a5,255
800003a4: 00700713 li a4,7
800003a8: fae79ce3 bne a5,a4,80000360 <trap+0x74>
800003ac: 02000793 li a5,32
800003b0: 1447a073 csrs sip,a5
800003b4: 08000793 li a5,128
800003b8: 3047b073 csrc mie,a5
800003bc: 01c12083 lw ra,28(sp)
800003c0: 01812403 lw s0,24(sp)
800003c4: 01412483 lw s1,20(sp)
800003c8: 01012903 lw s2,16(sp)
800003cc: 00c12983 lw s3,12(sp)
800003d0: 02010113 addi sp,sp,32
800003d4: 00008067 ret
800003d8: 341024f3 csrr s1,mepc
800003dc: 300025f3 csrr a1,mstatus
800003e0: 34302473 csrr s0,mtval
800003e4: 02f00613 li a2,47
800003e8: 07f47693 andi a3,s0,127
800003ec: 00c45713 srli a4,s0,0xc
800003f0: f6c684e3 beq a3,a2,80000358 <trap+0x6c>
800003f4: 07300613 li a2,115
800003f8: f6c694e3 bne a3,a2,80000360 <trap+0x74>
800003fc: 00377713 andi a4,a4,3
80000400: 12f70063 beq a4,a5,80000520 <trap+0x234>
80000404: 00300793 li a5,3
80000408: 10f70c63 beq a4,a5,80000520 <trap+0x234>
8000040c: 00100993 li s3,1
80000410: 03370463 beq a4,s3,80000438 <trap+0x14c>
80000414: 2a0000ef jal ra,800006b4 <stopSim>
80000418: 343027f3 csrr a5,mtval
8000041c: 14379073 csrw stval,a5
80000420: 341027f3 csrr a5,mepc
80000424: 14179073 csrw sepc,a5
80000428: 342027f3 csrr a5,mcause
8000042c: 14279073 csrw scause,a5
80000430: 105027f3 csrr a5,stvec
80000434: 34179073 csrw mepc,a5
80000438: 000017b7 lui a5,0x1
8000043c: 01445713 srli a4,s0,0x14
80000440: c0178693 addi a3,a5,-1023 # c01 <__stack_size+0x401>
80000444: 0ed70663 beq a4,a3,80000530 <trap+0x244>
80000448: c8178793 addi a5,a5,-895
8000044c: 0cf70463 beq a4,a5,80000514 <trap+0x228>
80000450: 264000ef jal ra,800006b4 <stopSim>
80000454: 343027f3 csrr a5,mtval
80000458: 14379073 csrw stval,a5
8000045c: 341027f3 csrr a5,mepc
80000460: 14179073 csrw sepc,a5
80000464: 342027f3 csrr a5,mcause
80000468: 14279073 csrw scause,a5
8000046c: 105027f3 csrr a5,stvec
80000470: 34179073 csrw mepc,a5
80000474: 1c099063 bnez s3,80000634 <trap+0x348>
80000478: 00545413 srli s0,s0,0x5
8000047c: 800017b7 lui a5,0x80001
80000480: f8878793 addi a5,a5,-120 # 80000f88 <_sp+0xffffff80>
80000484: 07c47413 andi s0,s0,124
80000488: 00f40433 add s0,s0,a5
8000048c: 01242023 sw s2,0(s0)
80000490: 00448493 addi s1,s1,4
80000494: 34149073 csrw mepc,s1
80000498: eedff06f j 80000384 <trap+0x98>
8000049c: 00d45713 srli a4,s0,0xd
800004a0: 01245793 srli a5,s0,0x12
800004a4: 800016b7 lui a3,0x80001
800004a8: f8868693 addi a3,a3,-120 # 80000f88 <_sp+0xffffff80>
800004ac: 07c77713 andi a4,a4,124
800004b0: 07c7f793 andi a5,a5,124
800004b4: 00d70733 add a4,a4,a3
800004b8: 00d787b3 add a5,a5,a3
800004bc: 00072703 lw a4,0(a4) # 20000 <__stack_size+0x1f800>
800004c0: 0007a603 lw a2,0(a5)
800004c4: 00020537 lui a0,0x20
800004c8: 30052073 csrs mstatus,a0
800004cc: 00000517 auipc a0,0x0
800004d0: 01850513 addi a0,a0,24 # 800004e4 <trap+0x1f8>
800004d4: 30551073 csrw mtvec,a0
800004d8: 00100793 li a5,1
800004dc: 00072803 lw a6,0(a4)
800004e0: 00000793 li a5,0
800004e4: 00020537 lui a0,0x20
800004e8: 30053073 csrc mstatus,a0
800004ec: 16079863 bnez a5,8000065c <trap+0x370>
800004f0: 01b45793 srli a5,s0,0x1b
800004f4: 01c00513 li a0,28
800004f8: e6f564e3 bltu a0,a5,80000360 <trap+0x74>
800004fc: 80000537 lui a0,0x80000
80000500: 00279793 slli a5,a5,0x2
80000504: 79450513 addi a0,a0,1940 # 80000794 <_sp+0xfffff78c>
80000508: 00a787b3 add a5,a5,a0
8000050c: 0007a783 lw a5,0(a5)
80000510: 00078067 jr a5
80000514: 1b8000ef jal ra,800006cc <rdtimeh>
80000518: 00050913 mv s2,a0
8000051c: f59ff06f j 80000474 <trap+0x188>
80000520: 00f45993 srli s3,s0,0xf
80000524: 01f9f993 andi s3,s3,31
80000528: 013039b3 snez s3,s3
8000052c: f0dff06f j 80000438 <trap+0x14c>
80000530: 194000ef jal ra,800006c4 <rdtime>
80000534: 00050913 mv s2,a0
80000538: f3dff06f j 80000474 <trap+0x188>
8000053c: 01067463 bgeu a2,a6,80000544 <trap+0x258>
80000540: 00080613 mv a2,a6
80000544: 00545413 srli s0,s0,0x5
80000548: 07c47413 andi s0,s0,124
8000054c: 00d406b3 add a3,s0,a3
80000550: 0106a023 sw a6,0(a3)
80000554: 000207b7 lui a5,0x20
80000558: 3007a073 csrs mstatus,a5
8000055c: 00000797 auipc a5,0x0
80000560: 01878793 addi a5,a5,24 # 80000574 <trap+0x288>
80000564: 30579073 csrw mtvec,a5
80000568: 00100693 li a3,1
8000056c: 00c72023 sw a2,0(a4)
80000570: 00000693 li a3,0
80000574: 000207b7 lui a5,0x20
80000578: 3007b073 csrc mstatus,a5
8000057c: 800007b7 lui a5,0x80000
80000580: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff074>
80000584: 0e069063 bnez a3,80000664 <trap+0x378>
80000588: 00448493 addi s1,s1,4
8000058c: 34149073 csrw mepc,s1
80000590: 30579073 csrw mtvec,a5
80000594: df1ff06f j 80000384 <trap+0x98>
80000598: 01064633 xor a2,a2,a6
8000059c: fa9ff06f j 80000544 <trap+0x258>
800005a0: 01060633 add a2,a2,a6
800005a4: fa1ff06f j 80000544 <trap+0x258>
800005a8: 01067633 and a2,a2,a6
800005ac: f99ff06f j 80000544 <trap+0x258>
800005b0: 01066633 or a2,a2,a6
800005b4: f91ff06f j 80000544 <trap+0x258>
800005b8: f8c876e3 bgeu a6,a2,80000544 <trap+0x258>
800005bc: 00080613 mv a2,a6
800005c0: f85ff06f j 80000544 <trap+0x258>
800005c4: f90650e3 bge a2,a6,80000544 <trap+0x258>
800005c8: 00080613 mv a2,a6
800005cc: f79ff06f j 80000544 <trap+0x258>
800005d0: f6c85ae3 bge a6,a2,80000544 <trap+0x258>
800005d4: 00080613 mv a2,a6
800005d8: f6dff06f j 80000544 <trap+0x258>
800005dc: fff00713 li a4,-1
800005e0: fae7a423 sw a4,-88(a5)
800005e4: 341027f3 csrr a5,mepc
800005e8: 00478793 addi a5,a5,4
800005ec: 34179073 csrw mepc,a5
800005f0: d95ff06f j 80000384 <trap+0x98>
800005f4: fac7a583 lw a1,-84(a5)
800005f8: 0dc000ef jal ra,800006d4 <setMachineTimerCmp>
800005fc: 08000793 li a5,128
80000600: 3047a073 csrs mie,a5
80000604: 02000793 li a5,32
80000608: 1447b073 csrc sip,a5
8000060c: 341027f3 csrr a5,mepc
80000610: 00478793 addi a5,a5,4
80000614: 34179073 csrw mepc,a5
80000618: d6dff06f j 80000384 <trap+0x98>
8000061c: 0ff57513 andi a0,a0,255
80000620: 09c000ef jal ra,800006bc <putC>
80000624: 341027f3 csrr a5,mepc
80000628: 00478793 addi a5,a5,4
8000062c: 34179073 csrw mepc,a5
80000630: d55ff06f j 80000384 <trap+0x98>
80000634: 080000ef jal ra,800006b4 <stopSim>
80000638: 343027f3 csrr a5,mtval
8000063c: 14379073 csrw stval,a5
80000640: 341027f3 csrr a5,mepc
80000644: 14179073 csrw sepc,a5
80000648: 342027f3 csrr a5,mcause
8000064c: 14279073 csrw scause,a5
80000650: 105027f3 csrr a5,stvec
80000654: 34179073 csrw mepc,a5
80000658: e21ff06f j 80000478 <trap+0x18c>
8000065c: 800007b7 lui a5,0x80000
80000660: 07c78793 addi a5,a5,124 # 8000007c <_sp+0xfffff074>
80000664: 30579073 csrw mtvec,a5
80000668: 343027f3 csrr a5,mtval
8000066c: 14379073 csrw stval,a5
80000670: 342027f3 csrr a5,mcause
80000674: 14279073 csrw scause,a5
80000678: 14149073 csrw sepc,s1
8000067c: 105027f3 csrr a5,stvec
80000680: 34179073 csrw mepc,a5
80000684: 10000793 li a5,256
80000688: 1007b073 csrc sstatus,a5
8000068c: 0035d793 srli a5,a1,0x3
80000690: 1007f793 andi a5,a5,256
80000694: 1007a073 csrs sstatus,a5
80000698: 000027b7 lui a5,0x2
8000069c: 80078793 addi a5,a5,-2048 # 1800 <__stack_size+0x1000>
800006a0: 3007b073 csrc mstatus,a5
800006a4: 000017b7 lui a5,0x1
800006a8: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
800006ac: 3007a073 csrs mstatus,a5
800006b0: cd5ff06f j 80000384 <trap+0x98>
800006b4 <stopSim>: 8000038c <writeWord>:
800006b4: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7fffeff4> 8000038c: 00020737 lui a4,0x20
800006b8: 00008067 ret 80000390: 30072073 csrs mstatus,a4
80000394: 00000717 auipc a4,0x0
80000398: 01870713 addi a4,a4,24 # 800003ac <writeWord+0x20>
8000039c: 30571073 csrw mtvec,a4
800003a0: 00100793 li a5,1
800003a4: 00b52023 sw a1,0(a0)
800003a8: 00000793 li a5,0
800003ac: 00020737 lui a4,0x20
800003b0: 30073073 csrc mstatus,a4
800003b4: 00078513 mv a0,a5
800003b8: 00008067 ret
800006bc <putC>: 800003bc <trap>:
800006bc: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7fffeff0> 800003bc: fe010113 addi sp,sp,-32
800006c0: 00008067 ret 800003c0: 00112e23 sw ra,28(sp)
800003c4: 00812c23 sw s0,24(sp)
800003c8: 00912a23 sw s1,20(sp)
800003cc: 01212823 sw s2,16(sp)
800003d0: 01312623 sw s3,12(sp)
800003d4: 342027f3 csrr a5,mcause
800003d8: 0807cc63 bltz a5,80000470 <trap+0xb4>
800003dc: 00200713 li a4,2
800003e0: 0ce78463 beq a5,a4,800004a8 <trap+0xec>
800003e4: 00900693 li a3,9
800003e8: 04d79463 bne a5,a3,80000430 <trap+0x74>
800003ec: 80001437 lui s0,0x80001
800003f0: 11040413 addi s0,s0,272 # 80001110 <_sp+0x0>
800003f4: fc442783 lw a5,-60(s0)
800003f8: 00100693 li a3,1
800003fc: fa842503 lw a0,-88(s0)
80000400: 2ed78863 beq a5,a3,800006f0 <trap+0x334>
80000404: 2ae78663 beq a5,a4,800006b0 <trap+0x2f4>
80000408: 2c078063 beqz a5,800006c8 <trap+0x30c>
8000040c: 01812403 lw s0,24(sp)
80000410: 01c12083 lw ra,28(sp)
80000414: 01412483 lw s1,20(sp)
80000418: 01012903 lw s2,16(sp)
8000041c: 00c12983 lw s3,12(sp)
80000420: 02010113 addi sp,sp,32
80000424: 35c0006f j 80000780 <stopSim>
80000428: 0076f693 andi a3,a3,7
8000042c: 14f68663 beq a3,a5,80000578 <trap+0x1bc>
80000430: 350000ef jal ra,80000780 <stopSim>
80000434: 343027f3 csrr a5,mtval
80000438: 14379073 csrw stval,a5
8000043c: 341027f3 csrr a5,mepc
80000440: 14179073 csrw sepc,a5
80000444: 342027f3 csrr a5,mcause
80000448: 14279073 csrw scause,a5
8000044c: 105027f3 csrr a5,stvec
80000450: 34179073 csrw mepc,a5
80000454: 01c12083 lw ra,28(sp)
80000458: 01812403 lw s0,24(sp)
8000045c: 01412483 lw s1,20(sp)
80000460: 01012903 lw s2,16(sp)
80000464: 00c12983 lw s3,12(sp)
80000468: 02010113 addi sp,sp,32
8000046c: 00008067 ret
80000470: 0ff7f793 andi a5,a5,255
80000474: 00700713 li a4,7
80000478: fae79ce3 bne a5,a4,80000430 <trap+0x74>
8000047c: 02000793 li a5,32
80000480: 1447a073 csrs sip,a5
80000484: 08000793 li a5,128
80000488: 3047b073 csrc mie,a5
8000048c: 01c12083 lw ra,28(sp)
80000490: 01812403 lw s0,24(sp)
80000494: 01412483 lw s1,20(sp)
80000498: 01012903 lw s2,16(sp)
8000049c: 00c12983 lw s3,12(sp)
800004a0: 02010113 addi sp,sp,32
800004a4: 00008067 ret
800004a8: 34102973 csrr s2,mepc
800004ac: 30002573 csrr a0,mstatus
800004b0: 34302473 csrr s0,mtval
800004b4: 80000737 lui a4,0x80000
800004b8: 07c70713 addi a4,a4,124 # 8000007c <_sp+0xffffef6c>
800004bc: 30571073 csrw mtvec,a4
800004c0: 02f00593 li a1,47
800004c4: 07f47613 andi a2,s0,127
800004c8: 00c45693 srli a3,s0,0xc
800004cc: f4b60ee3 beq a2,a1,80000428 <trap+0x6c>
800004d0: 07300713 li a4,115
800004d4: f4e61ee3 bne a2,a4,80000430 <trap+0x74>
800004d8: 0036f693 andi a3,a3,3
800004dc: 12f68063 beq a3,a5,800005fc <trap+0x240>
800004e0: 00300793 li a5,3
800004e4: 10f68c63 beq a3,a5,800005fc <trap+0x240>
800004e8: 00100993 li s3,1
800004ec: 03368463 beq a3,s3,80000514 <trap+0x158>
800004f0: 290000ef jal ra,80000780 <stopSim>
800004f4: 343027f3 csrr a5,mtval
800004f8: 14379073 csrw stval,a5
800004fc: 341027f3 csrr a5,mepc
80000500: 14179073 csrw sepc,a5
80000504: 342027f3 csrr a5,mcause
80000508: 14279073 csrw scause,a5
8000050c: 105027f3 csrr a5,stvec
80000510: 34179073 csrw mepc,a5
80000514: 000017b7 lui a5,0x1
80000518: 01445713 srli a4,s0,0x14
8000051c: c0178693 addi a3,a5,-1023 # c01 <__stack_size+0x401>
80000520: 0ed70663 beq a4,a3,8000060c <trap+0x250>
80000524: c8178793 addi a5,a5,-895
80000528: 0cf70463 beq a4,a5,800005f0 <trap+0x234>
8000052c: 254000ef jal ra,80000780 <stopSim>
80000530: 343027f3 csrr a5,mtval
80000534: 14379073 csrw stval,a5
80000538: 341027f3 csrr a5,mepc
8000053c: 14179073 csrw sepc,a5
80000540: 342027f3 csrr a5,mcause
80000544: 14279073 csrw scause,a5
80000548: 105027f3 csrr a5,stvec
8000054c: 34179073 csrw mepc,a5
80000550: 1a099c63 bnez s3,80000708 <trap+0x34c>
80000554: 00545413 srli s0,s0,0x5
80000558: 800017b7 lui a5,0x80001
8000055c: 09078793 addi a5,a5,144 # 80001090 <_sp+0xffffff80>
80000560: 07c47413 andi s0,s0,124
80000564: 00f40433 add s0,s0,a5
80000568: 00942023 sw s1,0(s0)
8000056c: 00490793 addi a5,s2,4
80000570: 34179073 csrw mepc,a5
80000574: ee1ff06f j 80000454 <trap+0x98>
80000578: 00d45693 srli a3,s0,0xd
8000057c: 01245793 srli a5,s0,0x12
80000580: 80001637 lui a2,0x80001
80000584: 09060613 addi a2,a2,144 # 80001090 <_sp+0xffffff80>
80000588: 07c6f693 andi a3,a3,124
8000058c: 07c7f793 andi a5,a5,124
80000590: 00c686b3 add a3,a3,a2
80000594: 00c787b3 add a5,a5,a2
80000598: 0006a683 lw a3,0(a3)
8000059c: 0007a583 lw a1,0(a5)
800005a0: 00020837 lui a6,0x20
800005a4: 30082073 csrs mstatus,a6
800005a8: 00000817 auipc a6,0x0
800005ac: 01880813 addi a6,a6,24 # 800005c0 <trap+0x204>
800005b0: 30581073 csrw mtvec,a6
800005b4: 00100793 li a5,1
800005b8: 0006a883 lw a7,0(a3)
800005bc: 00000793 li a5,0
800005c0: 00020837 lui a6,0x20
800005c4: 30083073 csrc mstatus,a6
800005c8: 16079463 bnez a5,80000730 <trap+0x374>
800005cc: 01b45793 srli a5,s0,0x1b
800005d0: 01c00813 li a6,28
800005d4: e4f86ee3 bltu a6,a5,80000430 <trap+0x74>
800005d8: 80001837 lui a6,0x80001
800005dc: 00279793 slli a5,a5,0x2
800005e0: 86c80813 addi a6,a6,-1940 # 8000086c <_sp+0xfffff75c>
800005e4: 010787b3 add a5,a5,a6
800005e8: 0007a783 lw a5,0(a5)
800005ec: 00078067 jr a5
800005f0: 1b0000ef jal ra,800007a0 <rdtimeh>
800005f4: 00050493 mv s1,a0
800005f8: f59ff06f j 80000550 <trap+0x194>
800005fc: 00f45993 srli s3,s0,0xf
80000600: 01f9f993 andi s3,s3,31
80000604: 013039b3 snez s3,s3
80000608: f0dff06f j 80000514 <trap+0x158>
8000060c: 18c000ef jal ra,80000798 <rdtime>
80000610: 00050493 mv s1,a0
80000614: f3dff06f j 80000550 <trap+0x194>
80000618: 0115f463 bgeu a1,a7,80000620 <trap+0x264>
8000061c: 00088593 mv a1,a7
80000620: 00545413 srli s0,s0,0x5
80000624: 07c47413 andi s0,s0,124
80000628: 00c40633 add a2,s0,a2
8000062c: 01162023 sw a7,0(a2)
80000630: 00020637 lui a2,0x20
80000634: 30062073 csrs mstatus,a2
80000638: 00000617 auipc a2,0x0
8000063c: 01860613 addi a2,a2,24 # 80000650 <trap+0x294>
80000640: 30561073 csrw mtvec,a2
80000644: 00100793 li a5,1
80000648: 00b6a023 sw a1,0(a3)
8000064c: 00000793 li a5,0
80000650: 00020637 lui a2,0x20
80000654: 30063073 csrc mstatus,a2
80000658: 0c079c63 bnez a5,80000730 <trap+0x374>
8000065c: 00490793 addi a5,s2,4
80000660: 34179073 csrw mepc,a5
80000664: 30571073 csrw mtvec,a4
80000668: dedff06f j 80000454 <trap+0x98>
8000066c: 0115c5b3 xor a1,a1,a7
80000670: fb1ff06f j 80000620 <trap+0x264>
80000674: 011585b3 add a1,a1,a7
80000678: fa9ff06f j 80000620 <trap+0x264>
8000067c: 0115f5b3 and a1,a1,a7
80000680: fa1ff06f j 80000620 <trap+0x264>
80000684: 0115e5b3 or a1,a1,a7
80000688: f99ff06f j 80000620 <trap+0x264>
8000068c: f8b8fae3 bgeu a7,a1,80000620 <trap+0x264>
80000690: 00088593 mv a1,a7
80000694: f8dff06f j 80000620 <trap+0x264>
80000698: f915d4e3 bge a1,a7,80000620 <trap+0x264>
8000069c: 00088593 mv a1,a7
800006a0: f81ff06f j 80000620 <trap+0x264>
800006a4: f6b8dee3 bge a7,a1,80000620 <trap+0x264>
800006a8: 00088593 mv a1,a7
800006ac: f75ff06f j 80000620 <trap+0x264>
800006b0: 0e0000ef jal ra,80000790 <getC>
800006b4: faa42423 sw a0,-88(s0)
800006b8: 341027f3 csrr a5,mepc
800006bc: 00478793 addi a5,a5,4
800006c0: 34179073 csrw mepc,a5
800006c4: d91ff06f j 80000454 <trap+0x98>
800006c8: fac42583 lw a1,-84(s0)
800006cc: 0dc000ef jal ra,800007a8 <setMachineTimerCmp>
800006d0: 08000793 li a5,128
800006d4: 3047a073 csrs mie,a5
800006d8: 02000793 li a5,32
800006dc: 1447b073 csrc sip,a5
800006e0: 341027f3 csrr a5,mepc
800006e4: 00478793 addi a5,a5,4
800006e8: 34179073 csrw mepc,a5
800006ec: d69ff06f j 80000454 <trap+0x98>
800006f0: 0ff57513 andi a0,a0,255
800006f4: 094000ef jal ra,80000788 <putC>
800006f8: 341027f3 csrr a5,mepc
800006fc: 00478793 addi a5,a5,4
80000700: 34179073 csrw mepc,a5
80000704: d51ff06f j 80000454 <trap+0x98>
80000708: 078000ef jal ra,80000780 <stopSim>
8000070c: 343027f3 csrr a5,mtval
80000710: 14379073 csrw stval,a5
80000714: 341027f3 csrr a5,mepc
80000718: 14179073 csrw sepc,a5
8000071c: 342027f3 csrr a5,mcause
80000720: 14279073 csrw scause,a5
80000724: 105027f3 csrr a5,stvec
80000728: 34179073 csrw mepc,a5
8000072c: e29ff06f j 80000554 <trap+0x198>
80000730: 30571073 csrw mtvec,a4
80000734: 343027f3 csrr a5,mtval
80000738: 14379073 csrw stval,a5
8000073c: 342027f3 csrr a5,mcause
80000740: 14279073 csrw scause,a5
80000744: 14191073 csrw sepc,s2
80000748: 105027f3 csrr a5,stvec
8000074c: 34179073 csrw mepc,a5
80000750: 10000793 li a5,256
80000754: 1007b073 csrc sstatus,a5
80000758: 00355793 srli a5,a0,0x3
8000075c: 1007f793 andi a5,a5,256
80000760: 1007a073 csrs sstatus,a5
80000764: 000027b7 lui a5,0x2
80000768: 80078793 addi a5,a5,-2048 # 1800 <__stack_size+0x1000>
8000076c: 3007b073 csrc mstatus,a5
80000770: 000017b7 lui a5,0x1
80000774: 88078793 addi a5,a5,-1920 # 880 <__stack_size+0x80>
80000778: 3007a073 csrs mstatus,a5
8000077c: cd9ff06f j 80000454 <trap+0x98>
800006c4 <rdtime>: 80000780 <stopSim>:
800006c4: fe002503 lw a0,-32(zero) # ffffffe0 <_sp+0x7fffefd8> 80000780: fe002e23 sw zero,-4(zero) # fffffffc <_sp+0x7fffeeec>
800006c8: 00008067 ret 80000784: 0000006f j 80000784 <stopSim+0x4>
800006cc <rdtimeh>: 80000788 <putC>:
800006cc: fe402503 lw a0,-28(zero) # ffffffe4 <_sp+0x7fffefdc> 80000788: fea02c23 sw a0,-8(zero) # fffffff8 <_sp+0x7fffeee8>
800006d0: 00008067 ret 8000078c: 00008067 ret
800006d4 <setMachineTimerCmp>: 80000790 <getC>:
800006d4: fec00793 li a5,-20 80000790: ff802503 lw a0,-8(zero) # fffffff8 <_sp+0x7fffeee8>
800006d8: fff00713 li a4,-1 80000794: 00008067 ret
800006dc: 00e7a023 sw a4,0(a5)
800006e0: fea02423 sw a0,-24(zero) # ffffffe8 <_sp+0x7fffefe0>
800006e4: 00b7a023 sw a1,0(a5)
800006e8: 00008067 ret
800006ec <__libc_init_array>: 80000798 <rdtime>:
800006ec: ff010113 addi sp,sp,-16 80000798: fe002503 lw a0,-32(zero) # ffffffe0 <_sp+0x7fffeed0>
800006f0: 00000797 auipc a5,0x0 8000079c: 00008067 ret
800006f4: 0a478793 addi a5,a5,164 # 80000794 <__init_array_end>
800006f8: 00812423 sw s0,8(sp) 800007a0 <rdtimeh>:
800006fc: 00000417 auipc s0,0x0 800007a0: fe402503 lw a0,-28(zero) # ffffffe4 <_sp+0x7fffeed4>
80000700: 09840413 addi s0,s0,152 # 80000794 <__init_array_end> 800007a4: 00008067 ret
80000704: 40f40433 sub s0,s0,a5
80000708: 00912223 sw s1,4(sp) 800007a8 <setMachineTimerCmp>:
8000070c: 01212023 sw s2,0(sp) 800007a8: fec00793 li a5,-20
80000710: 00112623 sw ra,12(sp) 800007ac: fff00713 li a4,-1
80000714: 40245413 srai s0,s0,0x2 800007b0: 00e7a023 sw a4,0(a5)
80000718: 00000493 li s1,0 800007b4: fea02423 sw a0,-24(zero) # ffffffe8 <_sp+0x7fffeed8>
8000071c: 00078913 mv s2,a5 800007b8: 00b7a023 sw a1,0(a5)
80000720: 04849263 bne s1,s0,80000764 <__libc_init_array+0x78> 800007bc: 00008067 ret
80000724: 955ff0ef jal ra,80000078 <_init>
80000728: 00000797 auipc a5,0x0 800007c0 <halInit>:
8000072c: 06c78793 addi a5,a5,108 # 80000794 <__init_array_end> 800007c0: 00008067 ret
80000730: 00000417 auipc s0,0x0
80000734: 06440413 addi s0,s0,100 # 80000794 <__init_array_end> 800007c4 <__libc_init_array>:
80000738: 40f40433 sub s0,s0,a5 800007c4: ff010113 addi sp,sp,-16
8000073c: 40245413 srai s0,s0,0x2 800007c8: 00000797 auipc a5,0x0
80000740: 00000493 li s1,0 800007cc: 0a478793 addi a5,a5,164 # 8000086c <__init_array_end>
80000744: 00078913 mv s2,a5 800007d0: 00812423 sw s0,8(sp)
80000748: 02849a63 bne s1,s0,8000077c <__libc_init_array+0x90> 800007d4: 00000417 auipc s0,0x0
8000074c: 00c12083 lw ra,12(sp) 800007d8: 09840413 addi s0,s0,152 # 8000086c <__init_array_end>
80000750: 00812403 lw s0,8(sp) 800007dc: 40f40433 sub s0,s0,a5
80000754: 00412483 lw s1,4(sp) 800007e0: 00912223 sw s1,4(sp)
80000758: 00012903 lw s2,0(sp) 800007e4: 01212023 sw s2,0(sp)
8000075c: 01010113 addi sp,sp,16 800007e8: 00112623 sw ra,12(sp)
80000760: 00008067 ret 800007ec: 40245413 srai s0,s0,0x2
80000764: 00249793 slli a5,s1,0x2 800007f0: 00000493 li s1,0
80000768: 00f907b3 add a5,s2,a5 800007f4: 00078913 mv s2,a5
8000076c: 0007a783 lw a5,0(a5) 800007f8: 04849263 bne s1,s0,8000083c <__libc_init_array+0x78>
80000770: 00148493 addi s1,s1,1 800007fc: 87dff0ef jal ra,80000078 <_init>
80000774: 000780e7 jalr a5 80000800: 00000797 auipc a5,0x0
80000778: fa9ff06f j 80000720 <__libc_init_array+0x34> 80000804: 06c78793 addi a5,a5,108 # 8000086c <__init_array_end>
8000077c: 00249793 slli a5,s1,0x2 80000808: 00000417 auipc s0,0x0
80000780: 00f907b3 add a5,s2,a5 8000080c: 06440413 addi s0,s0,100 # 8000086c <__init_array_end>
80000784: 0007a783 lw a5,0(a5) 80000810: 40f40433 sub s0,s0,a5
80000788: 00148493 addi s1,s1,1 80000814: 40245413 srai s0,s0,0x2
8000078c: 000780e7 jalr a5 80000818: 00000493 li s1,0
80000790: fb9ff06f j 80000748 <__libc_init_array+0x5c> 8000081c: 00078913 mv s2,a5
80000820: 02849a63 bne s1,s0,80000854 <__libc_init_array+0x90>
80000824: 00c12083 lw ra,12(sp)
80000828: 00812403 lw s0,8(sp)
8000082c: 00412483 lw s1,4(sp)
80000830: 00012903 lw s2,0(sp)
80000834: 01010113 addi sp,sp,16
80000838: 00008067 ret
8000083c: 00249793 slli a5,s1,0x2
80000840: 00f907b3 add a5,s2,a5
80000844: 0007a783 lw a5,0(a5)
80000848: 00148493 addi s1,s1,1
8000084c: 000780e7 jalr a5
80000850: fa9ff06f j 800007f8 <__libc_init_array+0x34>
80000854: 00249793 slli a5,s1,0x2
80000858: 00f907b3 add a5,s2,a5
8000085c: 0007a783 lw a5,0(a5)
80000860: 00148493 addi s1,s1,1
80000864: 000780e7 jalr a5
80000868: fb9ff06f j 80000820 <__libc_init_array+0x5c>

BIN
src/main/c/emulator/build/emulator.bin
View File

Binary file not shown.

2
src/main/c/emulator/src/config.h
View File

@ -4,6 +4,6 @@
//#define QEMU //#define QEMU
#define SIM #define SIM
#define OS_CALL 0xC0000000 #define OS_CALL 0xC0000000
#define DTB 0x81000000 #define DTB 0xC4000000
#endif #endif

27
src/main/c/emulator/src/hal.c
View File

@ -4,12 +4,17 @@
#ifdef SIM #ifdef SIM
void stopSim(){ void stopSim(){
*((volatile uint32_t*) 0xFFFFFFFC) = 0; *((volatile uint32_t*) 0xFFFFFFFC) = 0;
while(1);
} }
void putC(char c){ void putC(char c){
*((volatile uint32_t*) 0xFFFFFFF8) = c; *((volatile uint32_t*) 0xFFFFFFF8) = c;
} }
int32_t getC(){
return *((volatile int32_t*) 0xFFFFFFF8);
}
uint32_t rdtime(){ uint32_t rdtime(){
return *((volatile uint32_t*) 0xFFFFFFE0); return *((volatile uint32_t*) 0xFFFFFFE0);
} }
@ -27,14 +32,20 @@ void setMachineTimerCmp(uint32_t low, uint32_t high){
void halInit(){ void halInit(){
// putC('*');
// putC('*');
// putC('*');
// while(1){
// int32_t c = getC();
// if(c > 0) putC(c);
// }
} }
#endif #endif
#ifdef QEMU #ifdef QEMU
#define VIRT_CLINT 0x2000000 #define VIRT_CLINT 0x2000000
#define SIFIVE_TIMECMP_BASE VIRT_CLINT + 0x4000 #define SIFIVE_TIMECMP_BASE (VIRT_CLINT + 0x4000)
#define SIFIVE_TIME_BASE VIRT_CLINT + 0xBFF8 #define SIFIVE_TIME_BASE (VIRT_CLINT + 0xBFF8)
#define NS16550A_UART0_CTRL_ADDR 0x10000000 #define NS16550A_UART0_CTRL_ADDR 0x10000000
#define UART0_CLOCK_FREQ 32000000 #define UART0_CLOCK_FREQ 32000000
#define UART0_BAUD_RATE 115200 #define UART0_BAUD_RATE 115200
@ -95,7 +106,7 @@ static void ns16550a_init()
//} //}
void stopSim(){ void stopSim(){
*((volatile uint32_t*) 0xFFFFFFFC) = 0; while(1);
} }
void putC(char ch){ void putC(char ch){
@ -103,6 +114,14 @@ void putC(char ch){
uart[UART_THR] = ch & 0xff; uart[UART_THR] = ch & 0xff;
} }
int32_t getC(){
if (uart[UART_LSR] & UART_LSR_DA) {
return uart[UART_RBR];
} else {
return -1;
}
}
uint32_t rdtime(){ uint32_t rdtime(){
return *((volatile uint32_t*) SIFIVE_TIME_BASE); return *((volatile uint32_t*) SIFIVE_TIME_BASE);

1
src/main/c/emulator/src/hal.h
View File

@ -17,6 +17,7 @@
void halInit(); void halInit();
void stopSim(); void stopSim();
void putC(char c); void putC(char c);
int32_t getC();
uint32_t rdtime(); uint32_t rdtime();
uint32_t rdtimeh(); uint32_t rdtimeh();
void setMachineTimerCmp(uint32_t low, uint32_t high); void setMachineTimerCmp(uint32_t low, uint32_t high);

37
src/main/c/emulator/src/main.c
View File

@ -14,7 +14,22 @@ void putString(char* s){
} }
} }
void setup_pmp(void)
{
// Set up a PMP to permit access to all of memory.
// Ignore the illegal-instruction trap if PMPs aren't supported.
uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
asm volatile ("la t0, 1f\n\t"
"csrrw t0, mtvec, t0\n\t"
"csrw pmpaddr0, %1\n\t"
"csrw pmpcfg0, %0\n\t"
".align 2\n\t"
"1: csrw mtvec, t0"
: : "r" (pmpc), "r" (-1UL) : "t0");
}
void init() { void init() {
setup_pmp();
halInit(); halInit();
putString("*** VexRiscv BIOS ***\n"); putString("*** VexRiscv BIOS ***\n");
uint32_t sp = (uint32_t) (&_sp); uint32_t sp = (uint32_t) (&_sp);
@ -140,7 +155,27 @@ void trap(){
case CAUSE_ILLEGAL_INSTRUCTION:{ case CAUSE_ILLEGAL_INSTRUCTION:{
uint32_t mepc = csr_read(mepc); uint32_t mepc = csr_read(mepc);
uint32_t mstatus = csr_read(mstatus); uint32_t mstatus = csr_read(mstatus);
#ifdef SIM
uint32_t instruction = csr_read(mbadaddr); uint32_t instruction = csr_read(mbadaddr);
#endif
#ifdef QEMU
uint32_t instruction = 0;
uint32_t i;
if (mepc & 2) {
readWord(mepc - 2, &i);
i >>= 16;
if (i & 3 == 3) {
uint32_t u32Buf;
readWord(mepc+2, &u32Buf);
i |= u32Buf << 16;
}
} else {
readWord(mepc, &i);
}
instruction = i;
csr_write(mtvec, trapEntry); //Restore mtvec
#endif
uint32_t opcode = instruction & 0x7F; uint32_t opcode = instruction & 0x7F;
uint32_t funct3 = (instruction >> 12) & 0x7; uint32_t funct3 = (instruction >> 12) & 0x7;
switch(opcode){ switch(opcode){
@ -227,7 +262,7 @@ void trap(){
csr_write(mepc, csr_read(mepc) + 4); csr_write(mepc, csr_read(mepc) + 4);
}break; }break;
case SBI_CONSOLE_GETCHAR:{ case SBI_CONSOLE_GETCHAR:{
writeRegister(10, -1); //no char writeRegister(10, getC()); //no char
csr_write(mepc, csr_read(mepc) + 4); csr_write(mepc, csr_read(mepc) + 4);
}break; }break;
case SBI_SET_TIMER:{ case SBI_SET_TIMER:{

11
src/main/c/emulator/src/riscv.h
View File

@ -54,6 +54,17 @@
#define SSTATUS64_SD 0x8000000000000000 #define SSTATUS64_SD 0x8000000000000000
#define PMP_R 0x01
#define PMP_W 0x02
#define PMP_X 0x04
#define PMP_A 0x18
#define PMP_L 0x80
#define PMP_SHIFT 2
#define PMP_TOR 0x08
#define PMP_NA4 0x10
#define PMP_NAPOT 0x18
#define RDCYCLE 0xC00 //Read-only cycle Cycle counter for RDCYCLE instruction. #define RDCYCLE 0xC00 //Read-only cycle Cycle counter for RDCYCLE instruction.
#define RDTIME 0xC01 //Read-only time Timer for RDTIME instruction. #define RDTIME 0xC01 //Read-only time Timer for RDTIME instruction.
#define RDINSTRET 0xC02 //Read-only instret Instructions-retired counter for RDINSTRET instruction. #define RDINSTRET 0xC02 //Read-only instret Instructions-retired counter for RDINSTRET instruction.

42
src/main/scala/vexriscv/demo/Linux.scala
View File

@ -49,6 +49,13 @@ make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DH
make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=/home/miaou/Downloads/tmp/Image DTB=/home/miaou/Downloads/tmp/rv32.dtb RAMDISK=/home/miaou/Downloads/tmp/rootfs.cpio TRACE=no FLOW_INFO=yes TRACE_START=9570000099
@ -101,6 +108,37 @@ qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=/home/
make linux-dirclean linux-rebuild riscv-pk-dirclean riscv-pk-rebuild
qemu-system-riscv32 -M virt -kernel output/images/bbl -append "root=/dev/vda ro console=ttyS0" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic
qemu-system-riscv32 -M virt -kernel output/images/bbl -append "root=/dev/vda ro console=ttyS0" -drive file=output/images/rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -netdev user,id=net0 -device virtio-net-device,netdev=net0 -nographic -dtb virt.dtb
Compile
make spinal_vexriscv_sim_defconfig
make linux-dirclean linux-rebuild -j8; output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/vmlinux.bin
output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/vmlinux.bin
output/host/bin/riscv32-linux-objdump -S -d output/images/vmlinux > output/images/vmlinux.asm; split -b 1M output/images/vmlinux.asm
make clean
make spinal_vexriscv_sim_defconfig
make -j8; output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/vmlinux.bin
Run Qemu
qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=/home/miaou/pro/VexRiscv/src/main/c/emulator/build/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=board/spinal/vexriscv_sim/rv32.dtb,addr=0xC4000000 -device loader,file=output/images/vmlinux.bin,addr=0xC0000000 -device loader,file=output/images/rootfs.cpio,addr=0xc5000000
Run sim
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
make run DBUS=SIMPLE IBUS=SIMPLE SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=yes TRACE_START=9570000099
*/ */
@ -251,8 +289,8 @@ object LinuxGen {
) )
) )
if(withMmu) config.plugins += new MmuPlugin( if(withMmu) config.plugins += new MmuPlugin(
// virtualRange = a => True, virtualRange = a => True,
virtualRange = x => x(31 downto 24) =/= 0x81, //TODO It fix the DTB kernel access (workaround) // virtualRange = x => x(31 downto 24) =/= 0x81, //TODO It fix the DTB kernel access (workaround)
ioRange = (x => if(litex) x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF else x(31 downto 28) === 0xF), ioRange = (x => if(litex) x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF else x(31 downto 28) === 0xF),
allowUserIo = true allowUserIo = true
) )

91
src/test/cpp/regression/fail.gtkw
View File

@ -1,56 +1,63 @@
[*] [*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI [*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI
[*] Tue Jul 25 21:44:42 2017 [*] Sat Mar 30 09:33:33 2019
[*] [*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/debugPluginExternal.vcd" [dumpfile] "/home/miaou/pro/VexRiscv/src/test/cpp/regression/linux.vcd"
[dumpfile_mtime] "Tue Jul 25 21:44:34 2017" [dumpfile_mtime] "Sat Mar 30 09:16:30 2019"
[dumpfile_size] 961355289 [dumpfile_size] 249834424
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/regression/fail.gtkw" [savefile] "/home/miaou/pro/VexRiscv/src/test/cpp/regression/fail.gtkw"
[timestart] 3644000 [timestart] 106663042
[size] 1776 953 [size] 1920 1030
[pos] -775 -353 [pos] -458 -215
*-19.000000 4619595 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-5.000000 106541900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP. [treeopen] TOP.
[treeopen] TOP.VexRiscv. [treeopen] TOP.VexRiscv.
[treeopen] TOP.VexRiscv.mixedDivider_1. [sst_width] 287
[sst_width] 201 [signals_width] 465
[signals_width] 418
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 279 [sst_vpaned_height] 279
@28 @28
TOP.VexRiscv.DebugPlugin_haltIt TOP.VexRiscv.writeBack_arbitration_isFiring
@22 @22
TOP.VexRiscv.debug_bus_cmd_payload_address[7:0] TOP.VexRiscv.writeBack_PC[31:0]
TOP.VexRiscv.debug_bus_cmd_payload_data[31:0] TOP.VexRiscv.writeBack_INSTRUCTION[31:0]
@28 @28
TOP.VexRiscv.debug_bus_cmd_payload_wr TOP.VexRiscv.CsrPlugin_exception
TOP.VexRiscv.debug_bus_cmd_ready TOP.VexRiscv.CsrPlugin_privilege[1:0]
@22
TOP.VexRiscv.CsrPlugin_scause_exceptionCode[3:0]
@28
TOP.VexRiscv.CsrPlugin_scause_interrupt
@22
TOP.VexRiscv.IBusSimplePlugin_jump_pcLoad_payload[31:0]
@28
TOP.VexRiscv.IBusSimplePlugin_jump_pcLoad_valid
@22
TOP.VexRiscv.CsrPlugin_mepc[31:0]
TOP.VexRiscv.CsrPlugin_sepc[31:0]
@28
TOP.VexRiscv.decode_IS_RVC
@24
TOP.VexRiscv.CsrPlugin_mcycle[63:0]
@28
TOP.VexRiscv.decode_IS_RVC
TOP.VexRiscv.decode_arbitration_isValid
@22
TOP.VexRiscv.RegFilePlugin_regFile(10)[31:0]
@28
TOP.dBus_cmd_valid
TOP.dBus_cmd_ready
@22
TOP.dBus_cmd_payload_address[31:0]
@28
TOP.dBus_cmd_payload_wr
@29 @29
TOP.VexRiscv.debug_bus_cmd_valid TOP.dBus_cmd_payload_size[1:0]
@22 @22
TOP.VexRiscv.debug_bus_rsp_data[31:0] TOP.dBus_cmd_payload_data[31:0]
[color] 2 TOP.dBus_rsp_data[31:0]
TOP.VexRiscv.dBus_cmd_payload_address[31:0]
[color] 2
TOP.VexRiscv.dBus_cmd_payload_data[31:0]
@28 @28
[color] 2 TOP.dBus_rsp_error
TOP.VexRiscv.dBus_cmd_payload_size[1:0] TOP.dBus_rsp_ready
[color] 2
TOP.VexRiscv.dBus_cmd_payload_wr
[color] 2
TOP.VexRiscv.dBus_cmd_ready
[color] 2
TOP.VexRiscv.dBus_cmd_valid
@22
[color] 2
TOP.VexRiscv.dBus_rsp_data[31:0]
@28
[color] 2
TOP.VexRiscv.dBus_rsp_error
[color] 2
TOP.VexRiscv.dBus_rsp_ready
@22
TOP.VexRiscv.DebugPlugin_busReadDataReg[31:0]
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0

80
src/test/cpp/regression/main.cpp
View File

@ -3001,16 +3001,40 @@ public:
//#endif //#endif
#include <unistd.h>
#include <termios.h>
#include <fcntl.h>
void stdinNonBuffered(){
static struct termios old, new1;
tcgetattr(0, &old); /* grab old terminal i/o settings */
new1 = old; /* make new settings same as old settings */
new1.c_lflag &= ~ICANON; /* disable buffered i/o */
new1.c_lflag &= ~ECHO;
tcsetattr(0, TCSANOW, &new1); /* use these new terminal i/o settings now */
}
bool stdinNonEmpty(){
struct timeval tv;
fd_set fds;
tv.tv_sec = 0;
tv.tv_usec = 0;
FD_ZERO(&fds);
FD_SET(STDIN_FILENO, &fds);
select(STDIN_FILENO+1, &fds, NULL, NULL, &tv);
return (FD_ISSET(0, &fds));
}
#ifdef LINUX_SOC #ifdef LINUX_SOC
class LinuxSoc : public Workspace{ class LinuxSoc : public Workspace{
public: public:
LinuxSoc(string name) : Workspace(name) { LinuxSoc(string name) : Workspace(name) {
stdinNonBuffered();
} }
virtual bool isDBusCheckedRegion(uint32_t address){ return true;} virtual bool isDBusCheckedRegion(uint32_t address){ return true;}
virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xB0000000 || (addr & 0xE0000000) == 0xE0000000;} virtual bool isPerifRegion(uint32_t addr) { return (addr & 0xF0000000) == 0xB0000000 || (addr & 0xE0000000) == 0xE0000000;}
virtual bool isMmuRegion(uint32_t addr) { return (addr & 0xFF000000) != 0x81000000;} virtual bool isMmuRegion(uint32_t addr) { return true; }
virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) { virtual void dBusAccess(uint32_t addr,bool wr, uint32_t size,uint32_t mask, uint32_t *data, bool *error) {
if(isPerifRegion(addr)) switch(addr){ if(isPerifRegion(addr)) switch(addr){
@ -3024,7 +3048,15 @@ public:
cout << (char)*data; cout << (char)*data;
logTraces << (char)*data; logTraces << (char)*data;
logTraces.flush(); logTraces.flush();
} else fail(); } else {
if(stdinNonEmpty()){
char c;
read(0, &c, 1);
*data = c;
} else {
*data = -1;
}
}
break; break;
case 0xFFFFFFFC: fail(); break; //Simulation end case 0xFFFFFFFC: fail(); break; //Simulation end
default: cout << "Unmapped peripheral access : addr=0x" << hex << addr << " wr=" << wr << " mask=0x" << mask << " data=0x" << data << dec << endl; fail(); break; default: cout << "Unmapped peripheral access : addr=0x" << hex << addr << " wr=" << wr << " mask=0x" << mask << " data=0x" << data << dec << endl; fail(); break;
@ -3290,7 +3322,6 @@ static void multiThreadedExecute(queue<std::function<void()>> &lambdas){
} }
} }
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
#ifdef SEED #ifdef SEED
srand48(SEED); srand48(SEED);
@ -3317,14 +3348,49 @@ int main(int argc, char **argv, char **env) {
// ->run(0); // ->run(0);
//#endif //#endif
// {
// static struct termios old, new1;
// tcgetattr(0, &old); /* grab old terminal i/o settings */
// new1 = old; /* make new settings same as old settings */
// new1.c_lflag &= ~ICANON; /* disable buffered i/o */
// new1.c_lflag &= ~ECHO;
// tcsetattr(0, TCSANOW, &new1); /* use these new terminal i/o settings now */
// }
//
// std::string initialCommand;
//
// while(true){
// if(!inputAvailable()) {
// std::cout << "Waiting for input (Ctrl-C to cancel)..." << std::endl;
// sleep(1);
// } else {
// char c;
// read(0, &c, 1); printf("%d\n", c);
//// std::getline(std::cin, initialCommand);
// }
// }
//
// char c;
// while (1) { read(0, &c, 1); printf("%d\n", c); }
// while(true){
// char c = getchar();
// if(c > 0)
// {
// putchar(c);
// } else {
// putchar('*');
// sleep(500);
// }
// }
#ifdef LINUX_SOC #ifdef LINUX_SOC
LinuxSoc("linux") LinuxSoc("linux")
.withRiscvRef() .withRiscvRef()
->loadBin(EMULATOR, 0x80000000) ->loadBin(EMULATOR, 0x80000000)
->loadBin(DTB, 0x81000000) ->loadBin(VMLINUX, 0xC0000000)
->loadBin(VMLINUX, 0xc0000000) ->loadBin(DTB, 0xC4000000)
->loadBin(RAMDISK, 0xc2000000) ->loadBin(RAMDISK, 0xC5000000)
->setIStall(false) //TODO It currently improve speed but should be removed later ->setIStall(false) //TODO It currently improve speed but should be removed later
->setDStall(false) ->setDStall(false)
->bootAt(0x80000000) ->bootAt(0x80000000)

1
src/test/python/tool/disasm.s
View File

@ -1 +0,0 @@
.word 0x28488b3