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VexRiscv
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Remove the legacy pipelining from Axi4 cacheless bridges

This commit is contained in:
Charles Papon 2019-05-01 12:03:01 +02:00
parent 7d99a70e9c
commit c738246610
2 changed files with 8 additions and 23 deletions
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15
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -82,7 +82,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
slave(rsp)
}
def toAxi4Shared(stageCmd : Boolean = true): Axi4Shared = {
def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = {
val axi = Axi4Shared(DBusSimpleBus.getAxi4Config())
val pendingWritesMax = 7
val pendingWrites = CounterUpDown(
@ -92,7 +92,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
)
val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && !cmdPreFork.wr) || pendingWrites === pendingWritesMax))
val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && cmdPreFork.valid && !cmdPreFork.wr) || pendingWrites === pendingWritesMax))
axi.sharedCmd.arbitrationFrom(cmdFork)
axi.sharedCmd.write := cmdFork.wr
axi.sharedCmd.prot := "010"
@ -117,16 +117,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
axi.r.ready := True
axi.b.ready := True
//TODO remove
val axi2 = Axi4Shared(DBusSimpleBus.getAxi4Config())
axi.arw >-> axi2.arw
axi.w >> axi2.w
axi.r << axi2.r
axi.b << axi2.b
// axi2 << axi
axi2
axi
}
def toAxi4(stageCmd : Boolean = true) = this.toAxi4Shared(stageCmd).toAxi4()

16
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -68,7 +68,7 @@ object IBusSimpleBus{
}
case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle with IMasterSlave {
case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with IMasterSlave {
var cmd = Stream(IBusSimpleCmd())
var rsp = Flow(IBusSimpleRsp())
@ -79,7 +79,7 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
def toAxi4ReadOnly(): Axi4ReadOnly = {
assert(!interfaceKeepData)
assert(cmdIsPersistente)
val axi = Axi4ReadOnly(IBusSimpleBus.getAxi4Config())
axi.ar.valid := cmd.valid
@ -94,17 +94,11 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit
rsp.error := !axi.r.isOKAY()
axi.r.ready := True
//TODO remove
val axi2 = Axi4ReadOnly(IBusSimpleBus.getAxi4Config())
axi.ar >-> axi2.ar
axi.r << axi2.r
// axi2 << axi
axi2
axi
}
def toAvalon(): AvalonMM = {
assert(!interfaceKeepData)
assert(cmdIsPersistente)
val avalonConfig = IBusSimpleBus.getAvalonConfig()
val mm = AvalonMM(avalonConfig)
@ -199,7 +193,7 @@ class IBusSimplePlugin(resetVector : BigInt,
override def setup(pipeline: VexRiscv): Unit = {
super.setup(pipeline)
iBus = master(IBusSimpleBus(false)).setName("iBus")
iBus = master(IBusSimpleBus(cmdForkPersistence)).setName("iBus")
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.add(FENCE_I, Nil)