IBusCachedPlugin with twoStage config is now compatible with syncronous regfile
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9a4c35d7b6
commit
c83a157c64
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@ -23,6 +23,11 @@ trait Pipeline {
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filtered.head.asInstanceOf[T]
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}
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def serviceExist[T](clazz : Class[T]) = {
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val filtered = plugins.filter(o => clazz.isAssignableFrom(o.getClass))
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filtered.length != 0
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}
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def build(): Unit ={
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plugins.foreach(_.setup(this.asInstanceOf[T]))
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@ -24,6 +24,8 @@ class IBusCachedPlugin(config : InstructionCacheConfig) extends Plugin[VexRiscv]
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import config._
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var iBus : InstructionCacheMemBus = null
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object IBUS_ACCESS_ERROR extends Stageable(Bool)
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var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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@ -55,8 +57,11 @@ class IBusCachedPlugin(config : InstructionCacheConfig) extends Plugin[VexRiscv]
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cache.io.cpu.fetch.isStuck := fetch.arbitration.isStuck
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if(!twoStageLogic) cache.io.cpu.fetch.isStuckByOthers := fetch.arbitration.isStuckByOthers
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cache.io.cpu.fetch.address := fetch.output(PC)
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if(!twoStageLogic) fetch.arbitration.haltIt setWhen(cache.io.cpu.fetch.haltIt)
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if(!twoStageLogic) fetch.insert(INSTRUCTION) := cache.io.cpu.fetch.data
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if(!twoStageLogic) {
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fetch.arbitration.haltIt setWhen (cache.io.cpu.fetch.haltIt)
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fetch.insert(INSTRUCTION) := cache.io.cpu.fetch.data
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
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}
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cache.io.flush.cmd.valid := False
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@ -66,6 +71,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig) extends Plugin[VexRiscv]
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cache.io.cpu.decode.isStuck := decode.arbitration.isStuck
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cache.io.cpu.decode.address := decode.input(PC)
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decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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decode.insert(INSTRUCTION_ANTICIPATED) := cache.io.cpu.decode.dataAnticipated
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}
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@ -99,7 +105,7 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w
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val isStuck = Bool
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val isStuckByOthers = if(!p.twoStageLogic) Bool else null
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val address = UInt(p.addressWidth bit)
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val data = if(!p.twoStageLogic) Bits(32 bit) else null
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val data = Bits(32 bit) //If twoStageLogic == true, this signal is acurate only when there is the cache doesn't stall decode (Used for Sync regfile)
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val error = if(!p.twoStageLogic && p.catchAccessFault) Bool else null
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override def asMaster(): Unit = {
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@ -116,11 +122,12 @@ case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle
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val isStuck = Bool
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val address = UInt(p.addressWidth bit)
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val data = Bits(32 bit)
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val dataAnticipated = Bits(32 bits)
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val error = if(p.catchAccessFault) Bool else null
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override def asMaster(): Unit = {
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out(isValid, isStuck, address)
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in(haltIt, data)
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in(haltIt, data, dataAnticipated)
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if(p.catchAccessFault) in(error)
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}
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}
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@ -398,24 +405,30 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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fetchInstructionValidReg := False
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}
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io.cpu.fetch.data := fetchInstructionValue
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val decodeInstructionValid = Reg(Bool)
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val decodeInstructionReg = Reg(Bits(32 bits))
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val decodeInstructionRegIn = (!io.cpu.decode.isStuck) ? fetchInstructionValue | loadedWord.data
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io.cpu.decode.dataAnticipated := decodeInstructionReg
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when(!io.cpu.decode.isStuck){
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decodeInstructionValid := fetchInstructionValid
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decodeInstructionReg := fetchInstructionValue
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decodeInstructionReg := decodeInstructionRegIn
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io.cpu.decode.dataAnticipated := decodeInstructionRegIn
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}.elsewhen(loadedWord.valid && (loadedWord.address >> 2) === (io.cpu.decode.address >> 2)){
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decodeInstructionValid := True
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decodeInstructionReg := loadedWord.data
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decodeInstructionReg := decodeInstructionRegIn
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io.cpu.decode.dataAnticipated := decodeInstructionRegIn
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}
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io.cpu.decode.haltIt := io.cpu.decode.isValid && !decodeInstructionValid
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io.cpu.decode.data := decodeInstructionReg
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lineLoader.requestIn.valid := io.cpu.decode.isValid && !decodeInstructionValid
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lineLoader.requestIn.addr := io.cpu.decode.address
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}
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io.flush.cmd.ready := !(lineLoader.request.valid || io.cpu.fetch.isValid)
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@ -60,6 +60,7 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
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fetch.insert(INSTRUCTION) := iBus.rsp.inst
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fetch.insert(IBUS_ACCESS_ERROR) := iBus.rsp.error
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fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iBus.rsp.ready)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck,decode.input(INSTRUCTION),fetch.output(INSTRUCTION))
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if(catchAccessFault){
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decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
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@ -1,9 +1,11 @@
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package SpinalRiscv.Plugin
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import SpinalRiscv.{Stageable, DecoderService, Riscv, VexRiscv}
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import SpinalRiscv._
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable
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trait RegFileReadKind
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object ASYNC extends RegFileReadKind
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@ -41,7 +43,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,zeroBoot : Boolean = fals
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//read register file
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val srcInstruction = regFileReadyKind match{
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case `ASYNC` => input(INSTRUCTION)
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case `SYNC` => Mux(arbitration.isStuck,input(INSTRUCTION),fetch.output(INSTRUCTION))
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case `SYNC` => input(INSTRUCTION_ANTICIPATED)
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}
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val regFileReadAddress1 = srcInstruction(Riscv.rs1Range).asUInt
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@ -239,7 +239,7 @@ object TopLevel {
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.ASYNC,
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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@ -19,6 +19,7 @@ case class VexRiscvConfig(pcWidth : Int){
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object PC extends Stageable(UInt(pcWidth bits))
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object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(pcWidth bits))
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object INSTRUCTION extends Stageable(Bits(32 bits))
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object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits))
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object LEGAL_INSTRUCTION extends Stageable(Bool)
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object REGFILE_WRITE_VALID extends Stageable(Bool)
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object REGFILE_WRITE_DATA extends Stageable(Bits(32 bits))
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@ -1,19 +1,19 @@
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[*]
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[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
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[*] Sat Apr 8 15:08:01 2017
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[*] Sun Apr 9 09:10:08 2017
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[*]
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[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/rv32ui-p-simple.vcd"
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[dumpfile_mtime] "Sat Apr 8 15:02:54 2017"
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[dumpfile_size] 95378
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[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/rv32ui-p-addi.vcd"
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[dumpfile_mtime] "Sun Apr 9 09:08:48 2017"
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[dumpfile_size] 136439
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[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/fail.gtkw"
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[timestart] 211
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[timestart] 274
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[size] 1776 953
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[pos] -1 -1
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*-4.422177 320 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[pos] -775 -353
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*-2.774728 284 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.VexRiscv.
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[sst_width] 201
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[signals_width] 397
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[signals_width] 453
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[sst_expanded] 1
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[sst_vpaned_height] 279
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@800200
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@ -31,19 +31,18 @@ TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isValid
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TOP.VexRiscv.instructionCache_1.io_cpu_fetch_isStuck
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@22
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TOP.VexRiscv.instructionCache_1.io_cpu_fetch_address[31:0]
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TOP.VexRiscv.instructionCache_1.io_cpu_fetch_data[31:0]
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@1000200
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-fetch
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@800200
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-decode
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@28
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_isValid
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@29
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_haltIt
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@28
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_isStuck
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@22
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_address[31:0]
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_instruction[31:0]
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_data[31:0]
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@1000200
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-decode
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@800200
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@ -61,5 +60,28 @@ TOP.VexRiscv.instructionCache_1.io_mem_rsp_valid
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-ibus
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@28
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TOP.VexRiscv.instructionCache_1.clk
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@22
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TOP.VexRiscv.instructionCache_1.io_cpu_fetch_data[31:0]
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TOP.VexRiscv.decode_RegFilePlugin_srcInstruction[31:0]
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TOP.VexRiscv.instructionCache_1.io_cpu_decode_data[31:0]
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@29
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TOP.VexRiscv.decode_arbitration_isValid
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@28
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TOP.VexRiscv.decode_arbitration_isStuck
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@22
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TOP.VexRiscv.decode_PC[31:0]
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TOP.VexRiscv.decode_REG1[31:0]
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TOP.VexRiscv.decode_REG2[31:0]
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@28
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TOP.VexRiscv.decode_REG1_USE
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TOP.VexRiscv.decode_REG2_USE
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TOP.VexRiscv.decode_arbitration_isValid
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TOP.VexRiscv.decode_arbitration_isStuck
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@22
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TOP.VexRiscv.decode_RegFilePlugin_regFileReadAddress1[4:0]
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TOP.VexRiscv.decode_RegFilePlugin_regFileReadAddress2[4:0]
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TOP.VexRiscv.decode_RegFilePlugin_rs1Data[31:0]
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TOP.VexRiscv.decode_RegFilePlugin_rs2Data[31:0]
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TOP.VexRiscv.decode_RegFilePlugin_srcInstruction[31:0]
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[pattern_trace] 1
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[pattern_trace] 0
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