Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Better HexTools

This commit is contained in:
Dolu1990 2018-05-26 11:32:36 +02:00
parent b0777bc646
commit c8677cca9b
1 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/vexriscv/demo/MuraxUtiles.scala
View File

@ -74,7 +74,7 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
} }
object HexTools{ object HexTools{
def readHexFile(path : String, callback : (Int, Int) => Unit): Unit ={ def readHexFile(path : String, callback : (Int, Int) => Unit, offset : Int = 0): Unit ={
import scala.io.Source import scala.io.Source
def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16) def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
@ -87,7 +87,7 @@ object HexTools{
key match { key match {
case 0 => case 0 =>
for(i <- 0 until byteCount){ for(i <- 0 until byteCount){
callback(nextAddr + i, hToI(line, 9 + i * 2, 2)) callback(nextAddr + i + offset, hToI(line, 9 + i * 2, 2))
} }
case 2 => case 2 =>
offset = hToI(line, 9, 4) << 4 offset = hToI(line, 9, 4) << 4
@ -101,8 +101,6 @@ object HexTools{
} }
} }
def initRam[T <: Data](ram : Mem[T], onChipRamHexFile : String, ramOffset : BigInt): Unit ={ def initRam[T <: Data](ram : Mem[T], onChipRamHexFile : String, ramOffset : BigInt): Unit ={
val initContent = Array.fill[BigInt](ram.wordCount)(0) val initContent = Array.fill[BigInt](ram.wordCount)(0)
HexTools.readHexFile(onChipRamHexFile,(address,data) => { HexTools.readHexFile(onChipRamHexFile,(address,data) => {