Fetcher and IBusSimplePlugin flush reworked
This commit is contained in:
Charles Papon
parent
492310e6fa
commit
c94d8f1c6c
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@ -93,10 +93,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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class FetchArea(pipeline : VexRiscv) extends Area {
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import pipeline._
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import pipeline.config._
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val fetcherflushIt = stages.map(_.arbitration.flushNext).orR
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val externalFlush = stages.map(_.arbitration.flushNext).orR
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def getFlushAt(s : Any, lastCond : Boolean = true): Bool = {
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if(isDrivingDecode(s) && lastCond) pipeline.decode.arbitration.isRemoved else fetcherflushIt
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if(isDrivingDecode(s) && lastCond) pipeline.decode.arbitration.isRemoved else externalFlush
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}
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//Arbitrate jump requests into pcLoad
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@ -208,7 +208,6 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val input = Stream(UInt(32 bits))
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val output = Stream(UInt(32 bits))
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val halt = Bool()
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val flush = Bool()
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})
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stages(0).input << fetchPc.output
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@ -222,16 +221,16 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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fetchPc.redo.payload := stages.last.input.payload
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}
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stages.head.flush := False //getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
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val flush = (if(isDrivingDecode(IBUS_RSP)) pipeline.decode.arbitration.isRemoved || decode.arbitration.flushNext && !decode.arbitration.isStuck else externalFlush) || redoFetch
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for((s,sNext) <- (stages, stages.tail).zipped) {
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val discardInputOnFlush = s != stages.head
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sNext.flush := getFlushAt(IBUS_RSP, sNext == stages.last) || redoFetch
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val sFlushed = if(s != stages.head) flush else False
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val sNextFlushed = flush
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if(s == stages.head && pcRegReusedForSecondStage) {
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNext.flush, false, collapsBubble = false, flushInput = s.flush))
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNextFlushed, false, collapsBubble = false, flushInput = sFlushed))
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sNext.input.payload := fetchPc.pcReg
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fetchPc.pcRegPropagate setWhen(sNext.input.ready)
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} else {
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sNext.input << s.output.m2sPipeWithFlush(sNext.flush, false, collapsBubble = false, flushInput = s.flush)
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sNext.input << s.output.m2sPipeWithFlush(sNextFlushed, false, collapsBubble = false, flushInput = sFlushed)
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}
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}
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@ -294,14 +293,14 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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val injector = new Area {
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val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(fetcherflushIt))
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val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(externalFlush))
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if (injectorReadyCutGen) {
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iBusRsp.readyForError.clearWhen(inputBeforeStage.valid) //Can't emit error if there is a instruction pending in the s2mPipe
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incomingInstruction setWhen (inputBeforeStage.valid)
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}
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val decodeInput = (if (injectorStage) {
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val flushStage = getFlushAt(INJECTOR_M2S)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flushStage, false, collapsBubble = false, flushInput = fetcherflushIt)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flushStage, false, collapsBubble = false, flushInput = externalFlush)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid) //Can't emit error when there is a instruction pending in the injector stage buffer
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incomingInstruction setWhen (decodeInput.valid)
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@ -458,7 +457,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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val fetchContext = DynamicContext()
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fetchContext.hazard := hazard
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || externalFlush)
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object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._3
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@ -156,7 +156,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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stages(0).halt setWhen (cache.io.cpu.prefetch.haltIt)
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cache.io.cpu.fetch.isRemoved := fetcherflushIt
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cache.io.cpu.fetch.isRemoved := externalFlush
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}
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@ -255,7 +255,9 @@ class IBusSimplePlugin( resetVector : BigInt,
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val catchSomething = memoryTranslatorPortConfig != null || catchAccessFault
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var mmuBus : MemoryTranslatorBus = null
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if(rspHoldValue) assert(busLatencyMin <= 1)
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// if(rspHoldValue) assert(busLatencyMin <= 1)
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assert(!rspHoldValue, "rspHoldValue not supported yet")
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assert(!singleInstructionPipeline)
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override def setup(pipeline: VexRiscv): Unit = {
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super.setup(pipeline)
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@ -283,9 +285,12 @@ class IBusSimplePlugin( resetVector : BigInt,
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iBus.cmd << (if(cmdWithS2mPipe) cmd.s2mPipe() else cmd)
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//Avoid sending to many iBus cmd
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val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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val pendingCmdNext = pendingCmd + cmd.fire.asUInt - iBus.rsp.fire.asUInt
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pendingCmd := pendingCmdNext
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val pending = new Area{
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val inc, dec = Bool()
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val value = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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val next = value + U(inc) - U(dec)
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value := next
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}
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val secondStagePersistence = cmdForkPersistence && cmdForkOnSecondStage && !cmdWithS2mPipe
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def cmdForkStage = if(!secondStagePersistence) iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0) else iBusRsp.stages(1)
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@ -293,29 +298,30 @@ class IBusSimplePlugin( resetVector : BigInt,
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val cmdFork = if(!secondStagePersistence) new Area {
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//This implementation keep the cmd on the bus until it's executed or the the pipeline is flushed
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def stage = cmdForkStage
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stage.halt setWhen(stage.input.valid && (!cmd.valid || !cmd.ready))
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if(singleInstructionPipeline) {
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cmd.valid := stage.input.valid && pendingCmd =/= pendingMax && !stages.map(_.arbitration.isValid).orR
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assert(injectorStage == false)
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assert(iBusRsp.stages.dropWhile(_ != stage).length <= 2)
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}else {
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cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax
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}
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val canEmit = stage.output.ready && pending.value =/= pendingMax
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stage.halt setWhen(stage.input.valid && (!canEmit || !cmd.ready))
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cmd.valid := stage.input.valid && canEmit
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pending.inc := cmd.fire
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} else new Area{
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//This implementation keep the cmd on the bus until it's executed, even if the pipeline is flushed
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def stage = cmdForkStage
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val pendingFull = pendingCmd === pendingMax
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val cmdKeep = RegInit(False) setWhen(cmd.valid) clearWhen(cmd.ready)
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val pendingFull = pending.value === pendingMax
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val enterTheMarket = Bool()
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val cmdKeep = RegInit(False) setWhen(enterTheMarket) clearWhen(cmd.ready)
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val cmdFired = RegInit(False) setWhen(cmd.fire) clearWhen(stage.input.ready)
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stage.halt setWhen(cmd.isStall || (pendingFull && !cmdFired))
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cmd.valid := (stage.input.valid || cmdKeep) && !pendingFull && !cmdFired
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enterTheMarket := stage.input.valid && !pendingFull && !cmdFired && !cmdKeep
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// stage.halt setWhen(cmd.isStall || (pendingFull && !cmdFired)) //(cmd.isStall)
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stage.halt setWhen(pendingFull && !cmdFired && !cmdKeep)
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stage.halt setWhen(!cmd.ready && !cmdFired)
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cmd.valid := enterTheMarket || cmdKeep
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pending.inc := enterTheMarket
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}
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val mmu = (mmuBus != null) generate new Area {
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mmuBus.cmd.isValid := cmdForkStage.input.valid
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mmuBus.cmd.virtualAddress := cmdForkStage.input.payload
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mmuBus.cmd.bypassTranslation := False
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mmuBus.end := cmdForkStage.output.fire || fetcherflushIt
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mmuBus.end := cmdForkStage.output.fire || externalFlush
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cmd.pc := mmuBus.rsp.physicalAddress(31 downto 2) @@ U"00"
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@ -341,43 +347,37 @@ class IBusSimplePlugin( resetVector : BigInt,
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val rspJoin = new Area {
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import iBusRsp._
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//Manage flush for iBus transactions in flight
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt
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when(iBusRsp.stages.last.flush) {
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if(secondStagePersistence)
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discardCounter := pendingCmd + cmd.valid.asUInt - iBus.rsp.fire.asUInt
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else
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discardCounter := (if(cmdForkOnSecondStage) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt)
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}
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val rspBufferOutput = Stream(IBusSimpleRsp())
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val rspBuffer = if(!rspHoldValue) new Area{
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val rspBuffer = new Area {
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val output = Stream(IBusSimpleRsp())
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val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0))
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c.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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c.io.flush := iBusRsp.stages.last.flush
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if(compressedGen) c.io.flush setWhen(decompressor.consumeCurrent)
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if(!compressedGen && isDrivingDecode(IBUS_RSP)) c.io.flush setWhen(decode.arbitration.flushNext && iBusRsp.output.ready)
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rspBufferOutput << c.io.pop
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} else new Area{
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val rspStream = iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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val validReg = RegInit(False) setWhen(rspStream.valid) clearWhen(rspBufferOutput.ready)
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rspBufferOutput << rspStream
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rspBufferOutput.valid setWhen(validReg)
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt
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when(iBusRsp.flush) {
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discardCounter := (if(cmdForkOnSecondStage) pending.next else pending.value - U(pending.dec))
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}
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c.io.push << iBus.rsp.toStream
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// if(compressedGen) c.io.flush setWhen(decompressor.consumeCurrent)
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// if(!compressedGen && isDrivingDecode(IBUS_RSP)) c.io.flush setWhen(decode.arbitration.flushNext && iBusRsp.output.ready)
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val flush = discardCounter =/= 0 || iBusRsp.flush
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output.valid := c.io.pop.valid && discardCounter === 0
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output.payload := c.io.pop.payload
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c.io.pop.ready := output.ready || flush
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pending.dec := c.io.pop.fire // iBus.rsp.valid && flush || c.io.pop.valid && output.ready instead to avoid unecessary dependancies ?
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}
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val fetchRsp = FetchRsp()
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fetchRsp.pc := stages.last.output.payload
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fetchRsp.rsp := rspBufferOutput.payload
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fetchRsp.rsp.error.clearWhen(!rspBufferOutput.valid) //Avoid interference with instruction injection from the debug plugin
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fetchRsp.rsp := rspBuffer.output.payload
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fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin
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val join = Stream(FetchRsp())
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val exceptionDetected = False
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join.valid := stages.last.output.valid && rspBufferOutput.valid
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join.valid := stages.last.output.valid && rspBuffer.output.valid
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join.payload := fetchRsp
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stages.last.output.ready := stages.last.output.valid ? join.fire | join.ready
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rspBufferOutput.ready := join.fire
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rspBuffer.output.ready := join.fire
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output << join.haltWhen(exceptionDetected)
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if(memoryTranslatorPortConfig != null){
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