mirror of
https://github.com/SpinalHDL/VexRiscv.git
synced 2025-01-03 03:43:39 -05:00
update LrSc reservation logic to match the spec
This commit is contained in:
Dolu1990
parent
2dac7dae32
commit
c9bbf0d12a
9 changed files with 113 additions and 289 deletions
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@ -25,13 +25,16 @@ case class DataCacheConfig(cacheSize : Int,
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tagSizeShift : Int = 0, //Used to force infering ram
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withLrSc : Boolean = false,
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withAmo : Boolean = false,
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withSmp : Boolean = false,
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mergeExecuteMemory : Boolean = false){
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assert(!(mergeExecuteMemory && (earlyDataMux || earlyWaysHits)))
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assert(!(earlyDataMux && !earlyWaysHits))
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def burstSize = bytePerLine*8/memDataWidth
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val burstLength = bytePerLine/(memDataWidth/8)
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def catchSomething = catchUnaligned || catchIllegal || catchAccessError
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def withInternalAmo = withAmo && !withSmp
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def withInternalLrSc = withLrSc && !withSmp
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def withExternalLrSc = withLrSc && withSmp
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def getAxi4SharedConfig() = Axi4Config(
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addressWidth = addressWidth,
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dataWidth = memDataWidth,
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@ -133,15 +136,13 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
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val isWrite = Bool
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val data = Bits(p.cpuDataWidth bit)
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val address = UInt(p.addressWidth bit)
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val mmuException, unalignedAccess , accessError = Bool
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val clearLrsc = ifGen(p.withLrSc) {Bool}
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val mmuException, unalignedAccess, accessError = Bool
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// val exceptionBus = if(p.catchSomething) Flow(ExceptionCause()) else null
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override def asMaster(): Unit = {
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out(isValid,isStuck,isUser, address)
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in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite)
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outWithNull(clearLrsc)
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}
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}
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@ -169,11 +170,13 @@ case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{
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val data = Bits(p.memDataWidth bits)
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val mask = Bits(p.memDataWidth/8 bits)
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val length = UInt(log2Up(p.burstLength) bits)
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val exclusive = p.withSmp generate Bool()
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val last = Bool
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}
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case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{
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val data = Bits(p.memDataWidth bit)
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val error = Bool
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val exclusive = p.withSmp generate Bool()
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}
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case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave{
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@ -516,19 +519,17 @@ class DataCache(p : DataCacheConfig) extends Component{
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}
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val lrsc = withLrSc generate new Area{
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val lrSc = withLrSc generate new Area{
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val reserved = RegInit(False)
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when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && !io.cpu.redo && request.isLrsc && !request.wr){
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reserved := True
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}
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when(io.cpu.writeBack.clearLrsc){
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reserved := False
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when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.isLrsc
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&& !io.cpu.redo && !io.cpu.writeBack.mmuException && !io.cpu.writeBack.unalignedAccess && !io.cpu.writeBack.accessError){
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reserved := !request.wr
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}
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}
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val requestDataBypass = CombInit(request.data)
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val isAmo = if(withAmo) request.isAmo else False
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val amo = withAmo generate new Area{
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val internalAmo = withInternalAmo generate new Area{
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def rf = request.data
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def mem = dataMux
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@ -550,6 +551,7 @@ class DataCache(p : DataCacheConfig) extends Component{
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}
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val memCmdSent = RegInit(False) setWhen (io.mem.cmd.ready) clearWhen (!io.cpu.writeBack.isStuck)
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io.cpu.redo := False
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io.cpu.writeBack.accessError := False
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@ -564,9 +566,10 @@ class DataCache(p : DataCacheConfig) extends Component{
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io.mem.cmd.wr := request.wr
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io.mem.cmd.mask := mask
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io.mem.cmd.data := requestDataBypass
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if(withExternalLrSc) io.mem.cmd.exclusive := request.isLrsc || request.isAmo
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when(io.cpu.writeBack.isValid) {
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when(mmuRsp.isIoAccess) {
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when(mmuRsp.isIoAccess || (if(withExternalLrSc) request.isLrsc else False)) {
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io.cpu.writeBack.haltIt.clearWhen(request.wr ? io.mem.cmd.ready | io.mem.rsp.valid)
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io.mem.cmd.valid := !memCmdSent
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@ -574,7 +577,7 @@ class DataCache(p : DataCacheConfig) extends Component{
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io.mem.cmd.length := 0
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io.mem.cmd.last := True
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if(withLrSc) when(request.isLrsc && !lrsc.reserved){
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if(withInternalLrSc) when(request.isLrsc && !lrSc.reserved){
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io.mem.cmd.valid := False
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io.cpu.writeBack.haltIt := False
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}
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@ -595,7 +598,7 @@ class DataCache(p : DataCacheConfig) extends Component{
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io.cpu.writeBack.haltIt clearWhen(!request.wr || io.mem.cmd.ready)
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if(withAmo) when(isAmo){
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when(!amo.resultRegValid) {
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when(!internalAmo.resultRegValid) {
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io.mem.cmd.valid := False
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dataWriteCmd.valid := False
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io.cpu.writeBack.haltIt := True
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@ -608,7 +611,7 @@ class DataCache(p : DataCacheConfig) extends Component{
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if(withAmo) io.mem.cmd.valid := False
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}
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if(withLrSc) when(request.isLrsc && !lrsc.reserved){
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if(withInternalLrSc) when(request.isLrsc && !lrSc.reserved){
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io.mem.cmd.valid := False
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dataWriteCmd.valid := False
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io.cpu.writeBack.haltIt := False
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@ -648,12 +651,12 @@ class DataCache(p : DataCacheConfig) extends Component{
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if(withLrSc){
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when(request.isLrsc && request.wr){
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io.cpu.writeBack.data := (!lrsc.reserved).asBits.resized
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io.cpu.writeBack.data := (!lrSc.reserved).asBits.resized
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}
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}
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if(withAmo){
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when(request.isAmo){
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requestDataBypass := amo.resultReg
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requestDataBypass := internalAmo.resultReg
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}
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}
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}
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@ -254,7 +254,6 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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cache.io.cpu.writeBack.isStuck := arbitration.isStuck
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cache.io.cpu.writeBack.isUser := (if(privilegeService != null) privilegeService.isUser() else False)
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cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA))
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if(withLrSc) cache.io.cpu.writeBack.clearLrsc := service(classOf[IContextSwitching]).isContextSwitching
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redoBranch.valid := False
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redoBranch.payload := input(PC)
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@ -469,13 +469,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
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val atomic = withLrSc generate new Area{
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val reserved = RegInit(False)
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insert(ATOMIC_HIT) := reserved
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when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && !input(MEMORY_STORE)){
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reserved := True
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when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && !input(MMU_FAULT) && !skipCmd){
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reserved := !input(MEMORY_STORE)
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}
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when(service(classOf[IContextSwitching]).isContextSwitching){
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reserved := False
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}
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when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){
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skipCmd := True
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}
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@ -38,9 +38,9 @@ Disassembly of section .crt_section:
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80000060: 00d52023 sw a3,0(a0) # 10000000 <trap_entry-0x70000020>
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80000064: 18b5262f sc.w a2,a1,(a0)
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80000068: 00100713 li a4,1
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8000006c: 26e61e63 bne a2,a4,800002e8 <fail>
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8000006c: 14e61a63 bne a2,a4,800001c0 <fail>
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80000070: 00052703 lw a4,0(a0)
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80000074: 26e69a63 bne a3,a4,800002e8 <fail>
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80000074: 14e69663 bne a3,a4,800001c0 <fail>
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80000078: 00200e13 li t3,2
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8000007c: 10000537 lui a0,0x10000
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80000080: 00450513 addi a0,a0,4 # 10000004 <trap_entry-0x7000001c>
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@ -50,9 +50,9 @@ Disassembly of section .crt_section:
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80000090: 00d52023 sw a3,0(a0)
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80000094: 18b5262f sc.w a2,a1,(a0)
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80000098: 00100713 li a4,1
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8000009c: 24e61663 bne a2,a4,800002e8 <fail>
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8000009c: 12e61263 bne a2,a4,800001c0 <fail>
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800000a0: 00052703 lw a4,0(a0)
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800000a4: 24e69263 bne a3,a4,800002e8 <fail>
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800000a4: 10e69e63 bne a3,a4,800001c0 <fail>
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800000a8: 00300e13 li t3,3
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800000ac: 10000537 lui a0,0x10000
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800000b0: 00450513 addi a0,a0,4 # 10000004 <trap_entry-0x7000001c>
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@ -61,9 +61,9 @@ Disassembly of section .crt_section:
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800000bc: 06900693 li a3,105
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800000c0: 18b5262f sc.w a2,a1,(a0)
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800000c4: 00100713 li a4,1
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800000c8: 22e61063 bne a2,a4,800002e8 <fail>
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800000c8: 0ee61c63 bne a2,a4,800001c0 <fail>
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800000cc: 00052703 lw a4,0(a0)
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800000d0: 20e69c63 bne a3,a4,800002e8 <fail>
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800000d0: 0ee69863 bne a3,a4,800001c0 <fail>
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800000d4: 00400e13 li t3,4
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800000d8: 10000537 lui a0,0x10000
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800000dc: 00850513 addi a0,a0,8 # 10000008 <trap_entry-0x70000018>
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@ -73,10 +73,10 @@ Disassembly of section .crt_section:
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800000ec: 00d52023 sw a3,0(a0)
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800000f0: 100527af lr.w a5,(a0)
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800000f4: 18b5262f sc.w a2,a1,(a0)
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800000f8: 1ed79863 bne a5,a3,800002e8 <fail>
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800000fc: 1e061663 bnez a2,800002e8 <fail>
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800000f8: 0cd79463 bne a5,a3,800001c0 <fail>
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800000fc: 0c061263 bnez a2,800001c0 <fail>
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80000100: 00052703 lw a4,0(a0)
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80000104: 1ee59263 bne a1,a4,800002e8 <fail>
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80000104: 0ae59e63 bne a1,a4,800001c0 <fail>
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80000108: 00500e13 li t3,5
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8000010c: 10000537 lui a0,0x10000
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80000110: 00850513 addi a0,a0,8 # 10000008 <trap_entry-0x70000018>
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@ -85,133 +85,59 @@ Disassembly of section .crt_section:
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8000011c: 06f00693 li a3,111
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80000120: 00d52023 sw a3,0(a0)
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80000124: 18b5262f sc.w a2,a1,(a0)
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80000128: 1c061063 bnez a2,800002e8 <fail>
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80000128: 08060c63 beqz a2,800001c0 <fail>
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8000012c: 00052703 lw a4,0(a0)
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80000130: 1ae59c63 bne a1,a4,800002e8 <fail>
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80000134: 00600e13 li t3,6
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80000130: 08e69863 bne a3,a4,800001c0 <fail>
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80000134: 00700e13 li t3,7
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80000138: 10000537 lui a0,0x10000
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8000013c: 00c50513 addi a0,a0,12 # 1000000c <trap_entry-0x70000014>
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80000140: 07000593 li a1,112
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80000144: 07100613 li a2,113
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80000148: 07200693 li a3,114
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8000014c: 10000437 lui s0,0x10000
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80000150: 01040413 addi s0,s0,16 # 10000010 <trap_entry-0x70000010>
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80000154: 07300493 li s1,115
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80000158: 07400913 li s2,116
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8000015c: 07500993 li s3,117
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80000160: 00d52023 sw a3,0(a0)
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80000164: 01342023 sw s3,0(s0)
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80000168: 100527af lr.w a5,(a0)
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8000016c: 10042aaf lr.w s5,(s0)
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80000170: 18b5262f sc.w a2,a1,(a0)
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80000174: 1894292f sc.w s2,s1,(s0)
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80000178: 16d79863 bne a5,a3,800002e8 <fail>
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8000017c: 16061663 bnez a2,800002e8 <fail>
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80000180: 00052703 lw a4,0(a0)
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80000184: 16e59263 bne a1,a4,800002e8 <fail>
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80000188: 173a9063 bne s5,s3,800002e8 <fail>
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8000018c: 14091e63 bnez s2,800002e8 <fail>
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80000190: 00042a03 lw s4,0(s0)
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80000194: 15449a63 bne s1,s4,800002e8 <fail>
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80000198: 00700e13 li t3,7
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8000019c: 10000537 lui a0,0x10000
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800001a0: 01450513 addi a0,a0,20 # 10000014 <trap_entry-0x7000000c>
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800001a4: 07800593 li a1,120
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800001a8: 07900613 li a2,121
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800001ac: 07a00693 li a3,122
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800001b0: 01000e93 li t4,16
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8000013c: 01450513 addi a0,a0,20 # 10000014 <trap_entry-0x7000000c>
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80000140: 07800593 li a1,120
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80000144: 07900613 li a2,121
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80000148: 07a00693 li a3,122
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8000014c: 01000e93 li t4,16
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800001b4 <test7>:
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800001b4: 00d52023 sw a3,0(a0)
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800001b8: 100527af lr.w a5,(a0)
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800001bc: 18b5262f sc.w a2,a1,(a0)
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800001c0: 12d79463 bne a5,a3,800002e8 <fail>
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800001c4: 12061263 bnez a2,800002e8 <fail>
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800001c8: 00052703 lw a4,0(a0)
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800001cc: 10e59e63 bne a1,a4,800002e8 <fail>
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800001d0: fffe8e93 addi t4,t4,-1
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800001d4: 00450513 addi a0,a0,4
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800001d8: 00358593 addi a1,a1,3
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800001dc: 00360613 addi a2,a2,3
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800001e0: 00368693 addi a3,a3,3
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800001e4: fc0e98e3 bnez t4,800001b4 <test7>
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800001e8: 00900e13 li t3,9
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800001ec: 10000537 lui a0,0x10000
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800001f0: 10050513 addi a0,a0,256 # 10000100 <trap_entry-0x6fffff20>
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800001f4: 07b00593 li a1,123
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800001f8: 07c00613 li a2,124
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800001fc: 07d00693 li a3,125
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80000200: 00d52023 sw a3,0(a0)
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80000204: 100527af lr.w a5,(a0)
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80000208: 00000073 ecall
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8000020c: 18b5262f sc.w a2,a1,(a0)
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80000210: 00100713 li a4,1
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80000214: 0ce61a63 bne a2,a4,800002e8 <fail>
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80000218: 00052703 lw a4,0(a0)
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8000021c: 0ce69663 bne a3,a4,800002e8 <fail>
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80000220: 00b00e13 li t3,11
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80000224: 10000537 lui a0,0x10000
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80000228: 30050513 addi a0,a0,768 # 10000300 <trap_entry-0x6ffffd20>
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8000022c: 08200593 li a1,130
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80000230: 08300613 li a2,131
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80000234: 08400693 li a3,132
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80000238: 00d52023 sw a3,0(a0)
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8000023c: 00001eb7 lui t4,0x1
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80000240: 800e8e93 addi t4,t4,-2048 # 800 <trap_entry-0x7ffff820>
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80000244: 304e9073 csrw mie,t4
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80000248: 00800e93 li t4,8
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8000024c: 100527af lr.w a5,(a0)
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80000250: 300e9073 csrw mstatus,t4
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80000254: 00000013 nop
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80000258: 00000013 nop
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8000025c: 00000013 nop
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80000260: 00000013 nop
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80000264: 00000013 nop
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80000268: 00000013 nop
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8000026c: 18b5262f sc.w a2,a1,(a0)
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80000270: 00100713 li a4,1
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80000274: 06e61a63 bne a2,a4,800002e8 <fail>
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80000278: 00052703 lw a4,0(a0)
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8000027c: 06e69663 bne a3,a4,800002e8 <fail>
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80000280: 00c00e13 li t3,12
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80000284: 10000537 lui a0,0x10000
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80000288: 40050513 addi a0,a0,1024 # 10000400 <trap_entry-0x6ffffc20>
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8000028c: 08c00593 li a1,140
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80000290: 08d00613 li a2,141
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80000294: 08e00693 li a3,142
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80000298: 00d52023 sw a3,0(a0)
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8000029c: 00001eb7 lui t4,0x1
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800002a0: 800e8e93 addi t4,t4,-2048 # 800 <trap_entry-0x7ffff820>
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800002a4: 304e9073 csrw mie,t4
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800002a8: 00002eb7 lui t4,0x2
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800002ac: 808e8e93 addi t4,t4,-2040 # 1808 <trap_entry-0x7fffe818>
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800002b0: 100527af lr.w a5,(a0)
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800002b4: 300e9073 csrw mstatus,t4
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800002b8: 00000013 nop
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800002bc: 00000013 nop
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800002c0: 00000013 nop
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800002c4: 00000013 nop
|
||||
800002c8: 00000013 nop
|
||||
800002cc: 00000013 nop
|
||||
800002d0: 18b5262f sc.w a2,a1,(a0)
|
||||
800002d4: 00100713 li a4,1
|
||||
800002d8: 00e61863 bne a2,a4,800002e8 <fail>
|
||||
800002dc: 00052703 lw a4,0(a0)
|
||||
800002e0: 00e69463 bne a3,a4,800002e8 <fail>
|
||||
800002e4: 0100006f j 800002f4 <pass>
|
||||
80000150 <test7>:
|
||||
80000150: 00d52023 sw a3,0(a0)
|
||||
80000154: 100527af lr.w a5,(a0)
|
||||
80000158: 18b5262f sc.w a2,a1,(a0)
|
||||
8000015c: 06d79263 bne a5,a3,800001c0 <fail>
|
||||
80000160: 06061063 bnez a2,800001c0 <fail>
|
||||
80000164: 00052703 lw a4,0(a0)
|
||||
80000168: 04e59c63 bne a1,a4,800001c0 <fail>
|
||||
8000016c: fffe8e93 addi t4,t4,-1
|
||||
80000170: 00450513 addi a0,a0,4
|
||||
80000174: 00358593 addi a1,a1,3
|
||||
80000178: 00360613 addi a2,a2,3
|
||||
8000017c: 00368693 addi a3,a3,3
|
||||
80000180: fc0e98e3 bnez t4,80000150 <test7>
|
||||
80000184: 00900e13 li t3,9
|
||||
80000188: 10000537 lui a0,0x10000
|
||||
8000018c: 10050513 addi a0,a0,256 # 10000100 <trap_entry-0x6fffff20>
|
||||
80000190: 07b00593 li a1,123
|
||||
80000194: 07c00613 li a2,124
|
||||
80000198: 07d00693 li a3,125
|
||||
8000019c: 00d52023 sw a3,0(a0)
|
||||
800001a0: 100527af lr.w a5,(a0)
|
||||
800001a4: 00000073 ecall
|
||||
800001a8: 18b527af sc.w a5,a1,(a0)
|
||||
800001ac: 00000713 li a4,0
|
||||
800001b0: 00e79863 bne a5,a4,800001c0 <fail>
|
||||
800001b4: 00052703 lw a4,0(a0)
|
||||
800001b8: 00e59463 bne a1,a4,800001c0 <fail>
|
||||
800001bc: 0100006f j 800001cc <pass>
|
||||
|
||||
800002e8 <fail>:
|
||||
800002e8: f0100137 lui sp,0xf0100
|
||||
800002ec: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffc30>
|
||||
800002f0: 01c12023 sw t3,0(sp)
|
||||
800001c0 <fail>:
|
||||
800001c0: f0100137 lui sp,0xf0100
|
||||
800001c4: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffd58>
|
||||
800001c8: 01c12023 sw t3,0(sp)
|
||||
|
||||
800002f4 <pass>:
|
||||
800002f4: f0100137 lui sp,0xf0100
|
||||
800002f8: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffc2c>
|
||||
800002fc: 00012023 sw zero,0(sp)
|
||||
80000300: 00000013 nop
|
||||
80000304: 00000013 nop
|
||||
80000308: 00000013 nop
|
||||
8000030c: 00000013 nop
|
||||
80000310: 00000013 nop
|
||||
80000314: 00000013 nop
|
||||
800001cc <pass>:
|
||||
800001cc: f0100137 lui sp,0xf0100
|
||||
800001d0: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffd54>
|
||||
800001d4: 00012023 sw zero,0(sp)
|
||||
800001d8: 00000013 nop
|
||||
800001dc: 00000013 nop
|
||||
800001e0: 00000013 nop
|
||||
800001e4: 00000013 nop
|
||||
800001e8: 00000013 nop
|
||||
800001ec: 00000013 nop
|
||||
|
|
|
|||
|
|
@ -5,49 +5,30 @@
|
|||
:10003000938E0E8073900E3073002030F32E1034A8
|
||||
:10004000938E4E0073901E3473002030130E1000F8
|
||||
:100050003705001093054006130650069306600608
|
||||
:100060002320D5002F26B51813071000631EE6269F
|
||||
:1000700003270500639AE626130E200037050010BB
|
||||
:100060002320D5002F26B51813071000631AE614B5
|
||||
:10007000032705006396E614130E200037050010D1
|
||||
:100080001305450093057006130680069306900637
|
||||
:100090002320D5002F26B518130710006316E62479
|
||||
:1000A000032705006392E624130E30003705001085
|
||||
:100090002320D5002F26B518130710006312E6128F
|
||||
:1000A00003270500639EE610130E3000370500108D
|
||||
:1000B0001305450093057006130680069306900607
|
||||
:1000C0002F26B518130710006310E622032705003A
|
||||
:1000D000639CE620130E40003705001013058500D1
|
||||
:1000C0002F26B51813071000631CE60E0327050042
|
||||
:1000D0006398E60E130E40003705001013058500E7
|
||||
:1000E0009305A0061306B0069306C0062320D5008C
|
||||
:1000F000AF2705102F26B5186398D71E6316061E66
|
||||
:10010000032705006392E51E130E5000370500100B
|
||||
:1000F000AF2705102F26B5186394D70C6312060C92
|
||||
:1001000003270500639EE50A130E50003705001013
|
||||
:10011000130585009305D0061306E0069306F00646
|
||||
:100120002320D5002F26B5186310061C03270500D1
|
||||
:10013000639CE51A130E6000370500101305C50017
|
||||
:1001400093050007130610079306200737040010D5
|
||||
:10015000130404019304300713094007930950075F
|
||||
:100160002320D50023203401AF270510AF2A041027
|
||||
:100170002F26B5182F2994186398D71663160616DC
|
||||
:10018000032705006392E51663903A17631E09146E
|
||||
:10019000032A0400639A4415130E700037050010FB
|
||||
:1001A0001305450193058007130690079306A007E2
|
||||
:1001B000930E00012320D500AF2705102F26B51878
|
||||
:1001C0006394D7126312061203270500639EE5109D
|
||||
:1001D000938EFEFF13054500938535001306360008
|
||||
:1001E00093863600E3980EFC130E9000370500103E
|
||||
:1001F000130505109305B0071306C0079306D00733
|
||||
:100200002320D500AF270510730000002F26B51856
|
||||
:1002100013071000631AE60C032705006396E60C2B
|
||||
:10022000130EB000370500101305053093052008A4
|
||||
:1002300013063008930640082320D500B71E00009F
|
||||
:10024000938E0E8073904E30930E8000AF27051072
|
||||
:1002500073900E3013000000130000001300000024
|
||||
:100260001300000013000000130000002F26B51833
|
||||
:1002700013071000631AE606032705006396E606D7
|
||||
:10028000130EC00037050010130505409305C00884
|
||||
:100290001306D0089306E0082320D500B71E0000FF
|
||||
:1002A000938E0E8073904E30B72E0000938E8E800A
|
||||
:1002B000AF27051073900E301300000013000000EC
|
||||
:1002C00013000000130000001300000013000000E2
|
||||
:1002D0002F26B518130710006318E6000327050042
|
||||
:1002E0006394E6006F000001370110F0130141F242
|
||||
:1002F0002320C101370110F0130101F22320010076
|
||||
:1003000013000000130000001300000013000000A1
|
||||
:080310001300000013000000BF
|
||||
:100120002320D5002F26B518630C060803270500E9
|
||||
:100130006398E608130E700037050010130545019B
|
||||
:1001400093058007130690079306A007930E0001FE
|
||||
:100150002320D500AF2705102F26B5186392D706A8
|
||||
:100160006310060603270500639CE504938EFEFFDB
|
||||
:100170001305450093853500130636009386360037
|
||||
:10018000E3980EFC130E90003705001013050510C0
|
||||
:100190009305B0071306C0079306D0072320D500A8
|
||||
:1001A000AF27051073000000AF27B5181307000034
|
||||
:1001B0006398E700032705006394E5006F000001E2
|
||||
:1001C000370110F0130141F22320C101370110F073
|
||||
:1001D000130101F2232001001300000013000000AE
|
||||
:1001E00013000000130000001300000013000000C3
|
||||
:040000058000004C2B
|
||||
:00000001FF
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ _start:
|
|||
bne a1, a4, fail
|
||||
|
||||
|
||||
//Test 5 redo SC on reserved area should pass and should be written write memory
|
||||
//Test 5 redo SC on reserved area should fail
|
||||
li x28, 5
|
||||
li a0, 0x10000008
|
||||
li a1, 109
|
||||
|
|
@ -89,36 +89,10 @@ _start:
|
|||
li a3, 111
|
||||
sw a3, 0(a0)
|
||||
sc.w a2, a1, (a0)
|
||||
bne a2, x0, fail
|
||||
beq a2, x0, fail
|
||||
lw a4, 0(a0)
|
||||
bne a1, a4, fail
|
||||
bne a3, a4, fail
|
||||
|
||||
//Test 6 Allow two entries at the same time
|
||||
li x28, 6
|
||||
li a0, 0x1000000C
|
||||
li a1, 112
|
||||
li a2, 113
|
||||
li a3, 114
|
||||
li s0, 0x10000010
|
||||
li s1, 115
|
||||
li s2, 116
|
||||
li s3, 117
|
||||
|
||||
sw a3, 0(a0)
|
||||
sw s3, 0(s0)
|
||||
lr.w a5, (a0)
|
||||
lr.w s5, (s0)
|
||||
sc.w a2, a1, (a0)
|
||||
sc.w s2, s1, (s0)
|
||||
bne a5, a3, fail
|
||||
bne a2, x0, fail
|
||||
lw a4, 0(a0)
|
||||
bne a1, a4, fail
|
||||
|
||||
bne s5, s3, fail
|
||||
bne s2, x0, fail
|
||||
lw s4, 0(s0)
|
||||
bne s1, s4, fail
|
||||
|
||||
//Test 7 do a lot of allocation to clear the entries
|
||||
li x28, 7
|
||||
|
|
@ -157,7 +131,7 @@ test7:
|
|||
bne a5, a4, fail*/
|
||||
|
||||
|
||||
//Test 9 SC should fail after a context switching
|
||||
//Test 9 SC should pass after a context switching
|
||||
li x28, 9
|
||||
li a0, 0x10000100
|
||||
li a1, 123
|
||||
|
|
@ -166,11 +140,11 @@ test7:
|
|||
sw a3, 0(a0)
|
||||
lr.w a5, (a0)
|
||||
scall
|
||||
sc.w a2, a1, (a0)
|
||||
li a4, 1
|
||||
bne a2, a4, fail
|
||||
sc.w a5, a1, (a0)
|
||||
li a4, 0
|
||||
bne a5, a4, fail
|
||||
lw a4, 0(a0)
|
||||
bne a3, a4, fail
|
||||
bne a1, a4, fail
|
||||
|
||||
|
||||
|
||||
|
|
@ -192,58 +166,6 @@ test7:
|
|||
bne a7, a4, fail*/
|
||||
|
||||
|
||||
|
||||
//Test 11 SC should fail after a external interrupt context switching
|
||||
li x28, 11
|
||||
li a0, 0x10000300
|
||||
li a1, 130
|
||||
li a2, 131
|
||||
li a3, 132
|
||||
sw a3, 0(a0)
|
||||
li x29, 0x800 //800 external interrupts
|
||||
csrw mie,x29
|
||||
li x29, 0x008 //008 enable interrupts
|
||||
lr.w a5, (a0)
|
||||
csrw mstatus,x29 //Enable external interrupt (will jump instantly due to testbench setup)
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
sc.w a2, a1, (a0)
|
||||
li a4, 1
|
||||
bne a2, a4, fail
|
||||
lw a4, 0(a0)
|
||||
bne a3, a4, fail
|
||||
|
||||
|
||||
//Test 12 SC should fail after a external interrupt context switching (callback on lr)
|
||||
li x28, 12
|
||||
li a0, 0x10000400
|
||||
li a1, 140
|
||||
li a2, 141
|
||||
li a3, 142
|
||||
sw a3, 0(a0)
|
||||
li x29, 0x800 //800 external interrupts
|
||||
csrw mie,x29
|
||||
li x29, 0x1808 //008 enable interrupts
|
||||
lr.w a5, (a0)
|
||||
csrw mstatus,x29 //Enable external interrupt (will jump instantly due to testbench setup)
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
sc.w a2, a1, (a0)
|
||||
li a4, 1
|
||||
bne a2, a4, fail
|
||||
lw a4, 0(a0)
|
||||
bne a3, a4, fail
|
||||
|
||||
|
||||
|
||||
j pass
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -464,7 +464,6 @@ public:
|
|||
cout << hex << " a7=0x" << regs[17] << " a0=0x" << regs[10] << " a1=0x" << regs[11] << " a2=0x" << regs[12] << dec << endl;
|
||||
}
|
||||
#endif
|
||||
lrscReserved = false;
|
||||
//Check leguality of the interrupt
|
||||
if(interrupt) {
|
||||
bool hit = false;
|
||||
|
|
@ -835,7 +834,6 @@ public:
|
|||
status.mpie = 1;
|
||||
status.mpp = 0;
|
||||
pcWrite(mepc);
|
||||
lrscReserved = false;
|
||||
}break;
|
||||
case 0x10200073:{ //SRET
|
||||
if(privilege < 1){ ilegalInstruction(); return;}
|
||||
|
|
@ -844,7 +842,6 @@ public:
|
|||
status.spie = 1;
|
||||
status.spp = 0;
|
||||
pcWrite(sepc);
|
||||
lrscReserved = false;
|
||||
}break;
|
||||
case 0x00000073:{ //ECALL
|
||||
trap(0, 8+privilege, 0x00000073); //To follow the VexRiscv area saving implementation
|
||||
|
|
@ -909,6 +906,7 @@ public:
|
|||
if(hit){
|
||||
dWrite(pAddr, 4, i32_rs2);
|
||||
}
|
||||
lrscReserved = false;
|
||||
rfWrite(rd32, !hit);
|
||||
pcWrite(pc + 4);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -278,5 +278,4 @@ compile: verilate
|
|||
|
||||
clean:
|
||||
rm -rf obj_dir
|
||||
rm -f VexRiscv.v*.bin
|
||||
|
||||
|
|
|
|||
|
|
@ -436,7 +436,7 @@ class DBusDimension extends VexRiscvDimension("DBus") {
|
|||
cacheSize = 512 << r.nextInt(5)
|
||||
wayCount = 1 << r.nextInt(3)
|
||||
}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
|
||||
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "") + (if(earlyWaysHits) "Ewh " else "")) {
|
||||
new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "") + (if(earlyWaysHits) "Ewh " else "") + (if(withAmo) "Amo " else "")) {
|
||||
override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "") + (if(withAmo) "AMO=yes " else "")
|
||||
|
||||
override def applyOn(config: VexRiscvConfig): Unit = {
|
||||
|
|
|
|||
Loading…
Reference in a new issue