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VexRiscv
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LrSc align software model to the hardware. Linux OK

This commit is contained in:
Dolu1990 2020-04-05 21:45:45 +02:00
parent 2eec18de65
commit ca72a421be
1 changed files with 9 additions and 15 deletions
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18
src/test/cpp/regression/main.cpp
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@ -376,6 +376,7 @@ public:
bool lrscReserved; bool lrscReserved;
uint32_t lrscReservedAddress;
RiscvGolden() { RiscvGolden() {
pc = 0x80000000; pc = 0x80000000;
@ -891,6 +892,7 @@ public:
trap(0, 5, address); trap(0, 5, address);
} else { } else {
lrscReserved = true; lrscReserved = true;
lrscReservedAddress = pAddr;
rfWrite(rd32, data); rfWrite(rd32, data);
pcWrite(pc + 4); pcWrite(pc + 4);
} }
@ -902,7 +904,7 @@ public:
trap(0, 6, address); trap(0, 6, address);
} else { } else {
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; } if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
bool hit = lrscReserved; bool hit = lrscReserved && lrscReservedAddress == pAddr;
if(hit){ if(hit){
dWrite(pAddr, 4, i32_rs2); dWrite(pAddr, 4, i32_rs2);
} }
@ -1407,7 +1409,7 @@ public:
virtual void pass(){ throw success();} virtual void pass(){ throw success();}
virtual void fail(){ throw std::exception();} virtual void fail(){ throw std::exception();}
virtual void fillSimELements(); virtual void fillSimELements();
void dump(int i){ void dump(uint64_t i){
#ifdef TRACE #ifdef TRACE
if(i == TRACE_START && i != 0) cout << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "START TRACE" << endl; if(i == TRACE_START && i != 0) cout << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "**" << endl << "START TRACE" << endl;
if(i >= TRACE_START) tfp->dump(i); if(i >= TRACE_START) tfp->dump(i);
@ -2344,16 +2346,6 @@ public:
} }
virtual void preCycle(){ virtual void preCycle(){
VL_IN8(io_cpu_execute_isValid,0,0);
VL_IN8(io_cpu_execute_isStuck,0,0);
VL_IN8(io_cpu_execute_args_kind,0,0);
VL_IN8(io_cpu_execute_args_wr,0,0);
VL_IN8(io_cpu_execute_args_size,1,0);
VL_IN8(io_cpu_execute_args_forceUncachedAccess,0,0);
VL_IN8(io_cpu_execute_args_clean,0,0);
VL_IN8(io_cpu_execute_args_invalidate,0,0);
VL_IN8(io_cpu_execute_args_way,0,0);
if (top->dBus_cmd_valid && top->dBus_cmd_ready) { if (top->dBus_cmd_valid && top->dBus_cmd_ready) {
if(top->dBus_cmd_payload_wr){ if(top->dBus_cmd_payload_wr){
#ifndef SMP #ifndef SMP
@ -2378,9 +2370,11 @@ public:
ws->dBusAccess(top->dBus_cmd_payload_address + beat * 4,0,2,0,&rsp.data,&rsp.error); ws->dBusAccess(top->dBus_cmd_payload_address + beat * 4,0,2,0,&rsp.data,&rsp.error);
rsp.last = beat == top->dBus_cmd_payload_length; rsp.last = beat == top->dBus_cmd_payload_length;
#ifdef SMP #ifdef SMP
if(top->dBus_cmd_payload_exclusive){
rsp.exclusive = true; rsp.exclusive = true;
reservationValid = true; reservationValid = true;
reservationAddress = top->dBus_cmd_payload_address; reservationAddress = top->dBus_cmd_payload_address;
}
#endif #endif
rsps.push(rsp); rsps.push(rsp);
} }