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VexRiscv
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more smp cluster profiling

This commit is contained in:
Dolu1990 2020-05-12 13:25:55 +02:00
parent 63511b19a2
commit cb44a474fc
1 changed files with 14 additions and 8 deletions
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22
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -534,8 +534,11 @@ object VexRiscvSmpClusterOpenSbi extends App{
var reportTimer = 0 var reportTimer = 0
var reportCycle = 0 var reportCycle = 0
var dMemWrites, dMemWritesCached = 0l var dMemWrites, dMemWritesCached = 0l
var dMemWriteCacheAddress = 0l val dMemWriteCacheCtx = List(4,8,16,32,64).map(bytes => new {
val dMemWriteCacheMask = ~((1 << log2Up(128/8))-1) var counter = 0l
var address = 0l
val mask = ~((1 << log2Up(bytes))-1)
})
import java.io._ import java.io._
val csv = new PrintWriter(new File("bench.csv" )) val csv = new PrintWriter(new File("bench.csv" ))
@ -572,13 +575,16 @@ object VexRiscvSmpClusterOpenSbi extends App{
dMemWriteBytes += dut.io.dMem.cmd.length.toInt+1 dMemWriteBytes += dut.io.dMem.cmd.length.toInt+1
val address = dut.io.dMem.cmd.address.toLong val address = dut.io.dMem.cmd.address.toLong
dMemWrites += 1 dMemWrites += 1
if((address & dMemWriteCacheMask) == (dMemWriteCacheAddress & dMemWriteCacheMask)){ for(ctx <- dMemWriteCacheCtx){
dMemWritesCached += 1 if((address & ctx.mask) == (ctx.address & ctx.mask)){
} else { ctx.counter += 1
dMemWriteCacheAddress = address } else {
ctx.address = address
}
} }
}else { }else {
dMemReadBytes += dut.io.dMem.cmd.length.toInt+1 dMemReadBytes += dut.io.dMem.cmd.length.toInt+1
for(ctx <- dMemWriteCacheCtx) ctx.address = -1
} }
} }
reportTimer = reportTimer + 1 reportTimer = reportTimer + 1
@ -588,7 +594,7 @@ object VexRiscvSmpClusterOpenSbi extends App{
// println(f"\n** c=${reportCycle} ir=${iMemReadBytes*1e-6}%5.2f dr=${dMemReadBytes*1e-6}%5.2f dw=${dMemWriteBytes*1e-6}%5.2f **\n") // println(f"\n** c=${reportCycle} ir=${iMemReadBytes*1e-6}%5.2f dr=${dMemReadBytes*1e-6}%5.2f dw=${dMemWriteBytes*1e-6}%5.2f **\n")
csv.write(s"$reportCycle,$iMemReadBytes,$dMemReadBytes,$dMemWriteBytes,$iMemRequests,$iMemSequencial,$dMemWrites,$dMemWritesCached\n") csv.write(s"$reportCycle,$iMemReadBytes,$dMemReadBytes,$dMemWriteBytes,$iMemRequests,$iMemSequencial,$dMemWrites,${dMemWriteCacheCtx.map(_.counter).mkString(",")}\n")
csv.flush() csv.flush()
reportCycle = 0 reportCycle = 0
iMemReadBytes = 0 iMemReadBytes = 0
@ -597,7 +603,7 @@ object VexRiscvSmpClusterOpenSbi extends App{
iMemRequests = 0 iMemRequests = 0
iMemSequencial = 0 iMemSequencial = 0
dMemWrites = 0 dMemWrites = 0
dMemWritesCached = 0 for(ctx <- dMemWriteCacheCtx) ctx.counter = 0
} }
} }