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Litex cluster add DMA sel feature

This commit is contained in:
Dolu1990 2020-07-21 19:42:27 +02:00
parent 15bda15bc9
commit cc423cbe49
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -38,8 +38,9 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
val dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth val dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth
bridge.config.load(WishboneConfig( bridge.config.load(WishboneConfig(
addressWidth = 32 - log2Up(dataWidth / 8), addressWidth = 32 - log2Up(dataWidth / 8),
dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth, dataWidth = dataWidth,
useSTALL = true useSTALL = true,
selWidth = dataWidth/8
)) ))
interconnect.addConnection(bridge.bmb, dBusCoherent.bmb) interconnect.addConnection(bridge.bmb, dBusCoherent.bmb)
} }