Litex cluster add DMA sel feature

2020-07-21 19:42:27 +02:00 · 2020-07-21 19:42:27 +02:00 · cc423cbe49
parent 15bda15bc9
commit cc423cbe49
1 changed files with 3 additions and 2 deletions
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@ -38,8 +38,9 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
    val dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth
    bridge.config.load(WishboneConfig(
      addressWidth = 32 - log2Up(dataWidth / 8),
-      dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth,
-      useSTALL = true
+      dataWidth = dataWidth,
+      useSTALL = true,
+      selWidth = dataWidth/8
    ))
    interconnect.addConnection(bridge.bmb, dBusCoherent.bmb)
  }