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Fix d$ toAxi bridge

This commit is contained in:
Dolu1990 2021-09-02 14:14:42 +02:00
parent 5fc4125763
commit cc9f3e753a
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/ip/DataCache.scala
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@ -268,7 +268,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
}
def toAxi4Shared(stageCmd : Boolean = false, pendingWritesMax : Int = 7): Axi4Shared = {
val axi = Axi4Shared(p.getAxi4SharedConfig())
val axi = Axi4Shared(p.getAxi4SharedConfig()).setName("dbus_axi")
val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd
@ -289,7 +289,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
axi.sharedCmd.cache := "1111"
axi.sharedCmd.size := log2Up(p.memDataBytes)
axi.sharedCmd.addr := cmdStage.address
axi.sharedCmd.len := cmd.beatCountMinusOne.resized
axi.sharedCmd.len := cmdStage.beatCountMinusOne.resized
axi.writeData.arbitrationFrom(dataStage)
axi.writeData.data := dataStage.data