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VexRiscv
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Pipeline CSR isWrite

This commit is contained in:
Dolu1990 2018-02-26 10:19:33 +01:00
parent 2b6185b063
commit ccad64def5
1 changed files with 14 additions and 6 deletions
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20
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -208,6 +208,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
object ENV_CTRL extends Stageable(EnvCtrlEnum()) object ENV_CTRL extends Stageable(EnvCtrlEnum())
object IS_CSR extends Stageable(Bool) object IS_CSR extends Stageable(Bool)
object CSR_WRITE_OPCODE extends Stageable(Bool)
var allowInterrupts : Bool = null var allowInterrupts : Bool = null
var allowException : Bool = null var allowException : Bool = null
@ -530,6 +531,14 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
contextSwitching := jumpInterface.valid contextSwitching := jumpInterface.valid
//CSR read/write instructions management //CSR read/write instructions management
decode plug new Area{
import decode._
val imm = IMM(input(INSTRUCTION))
insert(CSR_WRITE_OPCODE) := (!((input(INSTRUCTION)(14 downto 13) === "01" && input(INSTRUCTION)(rs1Range) === 0)
|| (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0)))
}
execute plug new Area { execute plug new Area {
import execute._ import execute._
@ -551,10 +560,9 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
False -> writeSrc, False -> writeSrc,
True -> Mux(input(INSTRUCTION)(12), readDataReg & ~writeSrc, readDataReg | writeSrc) True -> Mux(input(INSTRUCTION)(12), readDataReg & ~writeSrc, readDataReg | writeSrc)
) )
val writeOpcode = (!((input(INSTRUCTION)(14 downto 13) === "01" && input(INSTRUCTION)(rs1Range) === 0)
|| (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0))) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
val writeInstruction = arbitration.isValid && input(IS_CSR) && writeOpcode val readInstruction = arbitration.isValid && input(IS_CSR) && !input(CSR_WRITE_OPCODE)
val readInstruction = arbitration.isValid && input(IS_CSR) && !writeOpcode
arbitration.haltItself setWhen(writeInstruction && !readDataRegValid) arbitration.haltItself setWhen(writeInstruction && !readDataRegValid)
val writeEnable = writeInstruction && !arbitration.isStuckByOthers && !arbitration.removeIt && readDataRegValid val writeEnable = writeInstruction && !arbitration.isStuckByOthers && !arbitration.removeIt && readDataRegValid
@ -575,8 +583,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
if(withRead && withWrite) { if(withRead && withWrite) {
illegalAccess := False illegalAccess := False
} else { } else {
if (withWrite) illegalAccess.clearWhen(writeOpcode) if (withWrite) illegalAccess.clearWhen(input(CSR_WRITE_OPCODE))
if (withRead) illegalAccess.clearWhen(!writeOpcode) if (withRead) illegalAccess.clearWhen(!input(CSR_WRITE_OPCODE))
} }
when(writeEnable) { when(writeEnable) {