Add VexRiscvAxi4 demo
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Dolu1990
parent
7c19288648
commit
ce6fd6d0aa
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@ -9,7 +9,7 @@ scalaVersion := "2.11.8"
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EclipseKeys.withSource := true
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libraryDependencies ++= Seq(
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.2",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.2",
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"com.github.spinalhdl" % "spinalhdl-core_2.11" % "0.11.3",
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"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "0.11.3",
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"org.yaml" % "snakeyaml" % "1.8"
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)
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@ -0,0 +1,190 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.Axi4ReadOnly
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import spinal.lib.bus.avalon.AvalonMM
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag}
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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/**
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* Created by spinalvm on 14.07.17.
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*/
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//class VexRiscvAvalon(debugClockDomain : ClockDomain) extends Component{
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//
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//}
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object VexRiscvAxi4WithIntegratedJtag{
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def main(args: Array[String]) {
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val report = SpinalVerilog{
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//CPU configuration
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val cpuConfig = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = false
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// ),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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)
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 6
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// )
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),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrielShifterPlugin,
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new MulPlugin,
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new DivPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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prediction = STATIC
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),
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new CsrPlugin(
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config = CsrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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mimpid = null,
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mhartid = null,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.NONE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ecallGen = false,
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wfiGen = false,
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ucycleAccess = CsrAccess.NONE
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)
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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//CPU instanciation
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val cpu = new VexRiscv(cpuConfig)
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//CPU modifications to be an Avalon one
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cpu.setDefinitionName("VexRiscvAxi4")
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cpu.rework {
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var iBus : Axi4ReadOnly = null
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for (plugin <- cpuConfig.plugins) plugin match {
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case plugin: IBusSimplePlugin => {
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plugin.iBus.asDirectionLess() //Unset IO properties of iBus
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iBus = master(plugin.iBus.toAxi4ReadOnly())
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.setName("iBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
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}
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case plugin: IBusCachedPlugin => {
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plugin.iBus.asDirectionLess() //Unset IO properties of iBus
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iBus = master(plugin.iBus.toAxi4ReadOnly())
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.setName("iBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
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}
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case plugin: DBusSimplePlugin => {
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plugin.dBus.asDirectionLess()
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master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
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.setName("dBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current))
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}
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case plugin: DBusCachedPlugin => {
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plugin.dBus.asDirectionLess()
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master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
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.setName("dBusAxi")
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.addTag(ClockDomainTag(ClockDomain.current))
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}
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case plugin: DebugPlugin => {
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plugin.io.bus.asDirectionLess()
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val jtag = slave(new Jtag())
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.setName("jtag")
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jtag <> plugin.io.bus.fromJtag()
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plugin.io.resetOut
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.addTag(ResetEmitterTag(plugin.debugClockDomain))
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.parent = null //Avoid the io bundle to be interpreted as a QSys conduit
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}
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case _ =>
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}
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for (plugin <- cpuConfig.plugins) plugin match {
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case plugin: CsrPlugin => {
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plugin.externalInterrupt
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.addTag(InterruptReceiverTag(iBus, ClockDomain.current))
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plugin.timerInterrupt
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.addTag(InterruptReceiverTag(iBus, ClockDomain.current))
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}
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case _ =>
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}
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}
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cpu
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}
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}
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}
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