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Litex smp cluster now blackboxify d$ data ram

This commit is contained in:
Dolu1990 2020-05-14 00:05:54 +02:00
parent 42fef8bbcd
commit cf60989ae1
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -329,7 +329,6 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
object VexRiscvLitexSmpClusterGen extends App { object VexRiscvLitexSmpClusterGen extends App {
val cpuCount = 4 val cpuCount = 4
val withStall = false
def parameter = VexRiscvLitexSmpClusterParameter( def parameter = VexRiscvLitexSmpClusterParameter(
cluster = VexRiscvSmpClusterParameter( cluster = VexRiscvSmpClusterParameter(
@ -350,8 +349,9 @@ object VexRiscvLitexSmpClusterGen extends App {
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")) debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
) )
SpinalVerilog(Bench.compressIo(dutGen)) val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
// SpinalVerilog(dutGen) // genConfig.generateVerilog(Bench.compressIo(dutGen))
genConfig.generateVerilog(dutGen)
} }