Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Litex smp cluster now blackboxify d$ data ram

This commit is contained in:
Dolu1990 2020-05-14 00:05:54 +02:00
parent 42fef8bbcd
commit cf60989ae1
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
View File

@ -329,7 +329,6 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
object VexRiscvLitexSmpClusterGen extends App {
val cpuCount = 4
val withStall = false
def parameter = VexRiscvLitexSmpClusterParameter(
cluster = VexRiscvSmpClusterParameter(
@ -350,8 +349,9 @@ object VexRiscvLitexSmpClusterGen extends App {
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
)
SpinalVerilog(Bench.compressIo(dutGen))
// SpinalVerilog(dutGen)
val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
// genConfig.generateVerilog(Bench.compressIo(dutGen))
genConfig.generateVerilog(dutGen)
}